Emerging Nanoelectronics: Life With and After CMOS
Adrian M. Ionescu and Kaustav Banerjee
Editors, Springer, ISBN: 1-4020-75332, 2004

1. "Thermal Challenges of 3-D ICs" (in Wafer Level 3-D ICs Process Technology)
   Sheng-Chih Lin and Kaustav Banerjee
   Editors: Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif, Springer,
   ISBN: 978-0-387-76532-7, 2008
    

2. "3D ICs DSM Interconnect Performance Modeling and Analysis” (in Interconnect Technology and Design for Gigascale Integration)
   S. Souri, T-Y. Chiang, P. Kapur, K. Banerjee and K. C. Saraswat
   Editors: Jeffrey A. Davis and James D. Meindl, Springer, ISBN: 1-4020-7606-1, 2003

1. Accurate Intrinsic Gate Capacitance Model for Carbon  Nanotube-Array Based FETs Considering Screening Effect                                                         Chaitanya Kshirsagar, Tom Kopley, Kaustav Banerjee   IEEE Electron Device Letters, 2008. (to appear)

2. A Design-Specific and Thermally-Aware Methodology for Trading-off Power and Performance in Leakage-Dominant CMOS Technologies
   Sheng-Chih Lin and Kaustav Banerjee
   IEEE Transactions on Very Large Scale Integration Systems, 2008. (to appear)

3. Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects
   Hong Li, Wen-Yan Yin, Kaustav Banerjee, and Jun-Fa Mao
   IEEE Transactions on Electron Devices, Vol. 55, No. 6, pp. 1328-1337, 2008 [] 

4. Cool Chips: Opportunities and Implications for Power and Thermal Management
   Sheng-Chih Lin and Kaustav Banerjee
   IEEE Transactions on Electron Devices, Special Issue on Device Technologies and Circuit   Techniques for Power Management, Vol. 55, No. 1, pp. 245-255,  2008 [] 

5. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II:  Implementation and  Implications for Power Estimation and Thermal  Management 
   Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee
   IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3351-3360, 2007 []

6. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model
   Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee
   IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3342-3350, 2007 []

7. A Statistical Framework for Estimation of Full-Chip Leakage Power Distribution under Parameter Variations
   Hamed Dadgour, Sheng-Chih Lin and Kaustav Banerjee
   IEEE Transactions on Electron Devices, Vol. 54, No. 11, pp. 2930-2945, 2007 [] 

8. 3D-Integration for Introspection
   Shashidhar Mysore, Banit Agrawal, Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee and Timothy Sherwood
   IEEE Micro: Micro's Top Picks from Computer Architecture Conferences (IEEE Micro - top pick), pp. 77-83, January-February 2007 []

9. Scaling Analysis of Multilevel Interconnect Temperatures for High Performance ICs
   Sungjun Im, Navin Srivastava, Kaustav Banerjee and Kenneth E. Goodson
   IEEE Transactions on Electron Devices, Vol. 52, No. 12, pp. 2710-2719, 2005 []

10. Supply and Power Optimization in Leakage Dominant Technologies
    Man Lung Mui, Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 9, pp. 1362-1371, 2005 []

11. Modeling and Analysis of Non-Uniform Substrate Temperature Effects on Global ULSI Interconnects
    Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, pp. 849-861, 2005 []

12. Mechanisms Leading to Erratic Snapback Behavior in Bipolar Junction Transistors with Base Emitter Shorted
    Amitabh Chatterjee, Ronald D. Schrimpf, Sameer Pendharkar and Kaustav Banerjee
    Journal of Applied Physics, Vol. 97, 084504, April 15, 2005 []

13. Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI
    Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
    International Journal of Analog Integrated Circuits and Signal Processing, Vol. 42, No. 3, pp. 277-290, Springer, 2005 []

14. Analytical Modelling of Single Electron Transistor (SET) for Hybrid CMOS-SET Analog IC Design
    Santanu Mahapatra, Vaibhav Vaish, Christoph Wasshuber, Kaustav Banerjee and Adrian Ionescu
    IEEE Transactions on Electron Devices, Vol. 51, No. 11, pp. 1772-1782, 2004 []

15. Interconnect Challenges for Nanoscale Electronic Circuits
    Navin Srivastava and Kaustav Banerjee
    TMS Journal of Materials (JOM), Special Issue on Nanoelectronics, Vol. 56, No. 10, pp. 30-31, October 2004 (INVITED) []

16. Modeling Techniques and Verification Methodologies for Substrate Coupling Effects in Mixed-Signal System-on-Chip Designs
    Adil Koukab, Kaustav Banerjee and Michel Declercq
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 6, pp. 823-836, 2004 []

17. A Global Interconnect Optimization Scheme for Nanometer Scale VLSI with Implications for Latency, Bandwidth and Power Dissipation
    Man Lung Mui, Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Electron Devices, Vol. 51, No. 2, pp. 195-203, February 2004 []

18. An Interconnect Scaling Scheme with Constant On-Chip Inductive Effects
    Kaustav Banerjee and Amit Mehrotra
    International Journal of Analog Integrated Circuits and Signal Processing, Vol. 35, pp. 97–105, 2003 []

19. Impact of Gate-to-Contact Spacing on ESD Performance of Salicided Deep Submicron NMOS Transistors
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Electron Devices, Vol. 49, No. 12, pp. 2183-2192, December 2002 []

20. Analysis of Nonuniform ESD Current Distribution in Deep Submicron NMOS Transistors
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Electron Devices, Vol. 49, No. 12, pp. 2171-2182, December 2002 []

21. A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs
    Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Electron Devices, Vol. 49, No. 11, pp. 2001-2007, November 2002 []

22. Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects
    Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 8, pp. 904-915, August 2002 []

23. Analysis and Design of Distributed ESD Protection Circuits for High-Speed Mixed-Signal and RF ICs
    Choshu Ito, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Electron Devices, Vol. 49, No. 8, pp. 1444-1454, August 2002 []

24. Investigation of Gate Bias Induced Heating Effect for the Robust Design of ESD Protection in a 0.13mm Salicided Technology
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Devices, Materials and Reliability. Vol. 2, No. 2, pp. 36-42, June 2002 []

25. A Quasi-Analytical SET Model for Few Electron Circuit Simulation
    Santanu Mahapatra, Adrian Mihai Ionescu and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 23, No. 6, pp. 366-368, June 2002 []

26. SET-based Quantiser Circuit for Digital Communications
    Santanu Mahapatra, Adrian Mihai Ionescu, Kaustav Banerjee and Michel Declercq
    IEE Electronics Letters, Vol. 38, No. 10, pp. 443-445, May 2002 []

27. Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effect
    Ting-Yen Chiang, Kaustav Banerjee and Krishna C. Saraswat
    IEEE Electron Device Letters, Vol. 23, No. 1, pp. 31-33, January 2002 []

28. Global (Interconnect) Warming
    Kaustav Banerjee and Amit Mehrotra
    IEEE Circuits and Devices Magazine, pp. 16-32, September 2001 (INVITED) []

29. 3-D ICs: A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-on-Chip Integration
    Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, and Krishna C. Saraswat
    Proceedings of the IEEE,  Special Issue, Interconnections- Addressing The Next Challenge of IC Technology, Vol. 89, No. 5, pp. 602-633, May 2001 (INVITED) []

30. Interconnect Limits on Gigascale Integration (GSI) in the 21st Century
    Jeffrey A. Davis, Raguraman Venkatesan, Alain Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, Rafael Reif, and James. D. Meindl
    Proceedings of the IEEE, Special Issue on Limits of Semiconductor Technology, Vol. 89, No. 3, pp. 305- 324, March 2001 (INVITED) []

31. Thermal Characteristics of Sub-Micron Vias Studied by Scanning Joule Expansion Microscopy
    Masanobu Igeta, Kaustav Banerjee, Guanghua Wu, Chenming Hu, and Arun Majumdar
    IEEE Electron Device Letters, Vol. 21, No. 5, pp. 224-226, May 2000 []

32. Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation
    Sven Rzepka, Kaustav Banerjee, Ekkehard Meusel, and Chenming Hu
    IEEE Transactions on Components, Packaging and Manufacturing Technology-A, vol. 21, No. 3, pp. 406-411, 1998 []

33. High-Current Failure Model for VLSI Interconnects Under Short-Pulse Stress Conditions
    Kaustav Banerjee, Ajith Amerasekera, Nathan Cheung, and Chenming Hu
    IEEE Electron Device Letters, vol. 18, No. 9, pp. 405-407, 1997 []

34. The Dependence of W-plug Via EM Performance on Via Size
    Huy A. Le, Kaustav Banerjee, and Joe W. McPherson
    Semiconductor Science and Technology, Vol. 11, pp. 858-864, 1996 []

1. Current Status and Future Perspectives of Carbon Nanotube Interconnects
   K.Banerjee, H. Li and N. Srivastava
   IEEE NANO: 8th International Conference on Nanotechnology, Arlington, TX, August 18-21, 2008. (INVITED)

2. Analysis and Implications of Parasitic and Screening Effects on the High-Frequency/RF Performance of Tunneling-Carbon Nanotube FETs                                    C. Kshirsagar, M. El-Zeftawi and K. Banerjee                  ACM Design Automation Conference (DAC), Anaheim, CA, June 8-13, 2008.

3. High-Frequency Effects in Carbon Nanotube Interconnects
   K. Banerjee, H. Li and N.Srivastava,
   12th IEEE Workshop on Signal Propagation on Interconnects (SPI), Avignon, Pope's Palace, France, May 12-15, 2008.
   (KEYNOTE)

4. 3D Device Modeling of Damage due to Filamentation under an ESD Event in Nanometer Scale Drain Extended NMOS (DE-NMOS)
   A. Chatterjee, S. Pendharkar, H. Gossner, C. Duvvury and K. Banerjee
   IEEE International Reliability Physics Symposium (IRPS), Phoenix, AZ, April 27-May 1, 2008.

5. High-Frequency Mutual Impedance Extraction of VLSI Interconnects in the Presence of a Multi-layer Conducting Substrate
   N. Srivastava, R. Suaya and K. Banerjee
   IEEE Design and Test in Europe (DATE), Munich, Germany, March 10-14, 2008.

6. Power and Thermal Management in the Nanometer Era
   K. Banerjee
   IEEE CPMT EDAPS, Taipei, Taiwan, December 15-17, 2007.  (INVITED)

7. Performance Analysis of Multi-Walled Carbon Nanotube Based Interconnects
   H. Li, W-Y. Yin, J-F. Mao and K. Banerjee
   IEEE International Semiconductor Device Research Symposium (ISDRS),College Park, MD, December 12-14, 2007.

8. Modeling and Analysis of Intrinsic Gate Capacitance for Carbon Nanotube Array Based Devices Considering Screening Effect and Diameter Variations  
   C. Kshirsagar, T. Kopley, and K. Banerjee  
   IEEE International Semiconductor Device Research Symposium (ISDRS),College Park, MD, December 12-14, 2007.

9. A Fast Semi-numerical Technique for the Solution of the Poisson-Boltzmann Equation in a Cylindrical Nanowire
   A. Ramu, M. P. Anantram and K. Banerjee
   IEEE International Semiconductor Device Research Symposium (ISDRS), College Park, MD, December 12-14, 2007.

10. Carbon Nanotube Vias: A Reality Check 
    H. Li, N. Srivastava, J-F. Mao, W-Y. Yin and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 10-12, 2007.

11. Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance
    S. Kolluri, K. Endo, E. Suzuki and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 10-12, 2007.

12. A Microscopic Understanding of DENMOS Device Failure Mechanism Under ESD Conditions
    A. Chatterjee, S. Pendharkar, Y-Y. Lin, C. Duvvury and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 10-12, 2007.

13. Nano-enhanced Architectures: Using Carbon Nanotube Interconnects in Cache Design 
    B. Agrawal, N. Srivastava, F. T. Chong, K. Banerjee and T. Sherwood
    4th Workshop on Non-Silicon Computing (NSC-4) held in conjunction with the International     Symposium on Computer Architecture (ISCA'07 workshop), San Diego, California, June 2007.

14. Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications
    H. F. Dadgour and K. Banerjee  
    ACM Design Automation Conference (DAC), San Diego, CA, June 4-8, 2007.

15. An Insight into the High Current ESD Behavior of Drain Extended NMOS (DENMOS) Devices in Nanometer Scale CMOS Technologies  
    A. Chatterjee, S. Pendharkar, Y-Y Lin, C. Duvvury and K. Banerjee  
    IEEE International Reliability Physics Symposium (IRPS), Phoenix, Arizona, April 15-19, 2007.

16. Thermal Modeling and Thermal-Aware Design in Nanometer Technologies 
    K. Banerjee, E. Pop and M. Stan 
    17th ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa-Lago Maggiore, Italy, March 11-13, 2007.  (TUTORIAL)

17. SoC Communication Architectures: Technology, Current Practice, Research and Trends
    N. Dutt, K. Banerjee, L. Benini, K. Lahiri and S. Pasricha
    VLSI Design Conference, Bangalore, India, January 6-10, 2007. (TUTORIAL)

18. Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections?
    K. Banerjee
    IEEE-CPMT Electrical Design of Advanced Packaging Systems (EDAPS), Shanghai, China, December 17-19, 2006.  (INVITED)

19. Power and Thermal Challenges for 65 nm and Below
    K. Banerjee, P. Coteus and V. De
    IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 5-9, 2006. (INVITED TUTORIAL)

20. An Electrothermally-Aware Full-Chip Substrate Temperature Gradient Evaluation Methodology for Leakage Dominant Technologies with Implications for Power Estimation and Hot-Spot Management
    S-C. Lin and K. Banerjee
    IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 5-9, 2006, pp. 568-574 .[]  

21. Carbon Nanotubes: An Emerging Alternative for On-Chip VLSI Interconnects
    Kaustav Banerjee
    Future Directions in IC and Package Design Workshop, (FDIP)/IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), Scottsdale, Arizona, October 22, 2006. (INVITED)

22. Introspective 3D Chips
    S. C. Mysore, B. Agarwal, N. Srivastava, S-C. Lin, K. Banerjee  and T. Sherwood
    International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), San Jose, California, October 21-25, 2006, pp. 264-273. [] IEEE MICRO Top Pick

23. Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities
    R. Suaya, R. Escovar, S. Ortiz, K. Banerjee and N. Srivastava
    23rd Advanced Metallization Conference, San Diego, California, October 16-19, 2006. [] (INVITED)

24. Prospects for Carbon Nanotube Interconnects
    K. Banerjee
    23rd Advanced Metallization Conference, San Diego, California, October 16-19, 2006  (INVITED)

25. Thermal Dissipation in Multilayer Devices
    R. V. Joshi, K. Banerjee, T. Smy, K. Guarini, C.T. Chuang and N. Zamadmar
    23rd Advanced Metallization Conference, San Diego, California, October 16-19, 2006  (INVITED)

26. Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections?
    K. Banerjee, S. Im and N. Srivastava
    IEEE Conference on Nano Networks (Nano-Net), Lausanne, Switzerland, Sept. 14-16, 2006.  (INVITED)

27. Are Carbon Nanotubes the Future of VLSI Interconnections ?
    K. Banerjee and N. Srivastava
    ACM Design Automation Conference (DAC), San Francisco, California, July 24-28, 2006, pp. 809-814.[]  (INVITED)

28. A Novel Variation-Aware Low-Power Keeper Architecture for Wide Fan-in Dynamic Gates
    H. F. Dadgour, R. V. Joshi and K. Banerjee
    ACM Design Automation Conference (DAC), San Francisco, California, July 24-28, 2006, pp. 977-982. []

29. A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy
    G.L. Loi, B. Agrawal, N. Srivastava, S-C Lin, T. Sherwood and K. Banerjee
    ACM Design Automation Conference (DAC), San Francisco, California, July 24-28, 2006, pp. 991-996. []

30. Emerging Interconnect Technologies Based on Carbon Nanotubes
    N. Srivastava and K. Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, California, March 27-29, 2006. (INVITED Tutorial)

31. Electrothermal Engineering in the Nanometer Era: From Devices and Interconnects to Circuits and Systems
    K. Banerjee, S-C. Lin, and N. Srivastava
    Proceedings of the 11th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 24-27, Yokohama, Japan , 2006. (INVITED) []

32. Analysis and Implications of IC Cooling for Deep Nanometer Scale CMOS Technologies
    S-C. Lin, R. Mahajan, V. De and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 5-7, 2005, pp. 1041-1044. []
    HIGHLIGHTED PAPER OF IEDM 2005

33. Carbon Nanotube Interconnects: Implications for Performance, Power Dissipation and Thermal Management
    N. Srivastava, R. V. Joshi and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 5-7, 2005, pp. 257-260. []

34. New Physical Insight and Modeling of Second Breakdown (It2) Phenomenon in Advanced ESD Protection Devices
    A. Chatterjee, C. Duvvury and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 5-7, 2005, pp. 203-206. []

35. Performance Analysis of Carbon Nanotube Interconnects for VLSI Applications
    N. Srivastava and K. Banerjee
    IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 6-10, 2005, pp. 383-390. []

36. Thermal Scaling Analysis of Multilevel Cu/Low-k Interconnect Structures in Deep Nanometer Scale Technologies
    S. Im, N. Srivastava, K. Banerjee and K. E. Goodson
    Proceedings of the 22nd International VLSI Multilevel Interconnect Conference (VMIC), Fremont, CA, October 3-6, 2005, pp. 525-530. []
    OUTSTANDING STUDENT PAPER AWARD

37. A Thermally Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs
    S-C. Lin, N. Srivastava and K. Banerjee
    International Conference on Computer Design (ICCD), San Jose, October 2-5, 2005, pp. 411-416. []

38. Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond
    K. Banerjee, S. Im and N. Srivastava
    Proceedings of the 22nd Advanced Metallization Conference (AMC), Colorado Springs, CO, September 27-29, 2005 (INVITED) []

39. Thermal Modeling of Bonded SOI/3D ICs
    R. V. Joshi, K. Banerjee, T. Smy, K. Guarini, C. T. Chuang, A. Devgan and N. Zamadmar
    Advanced Metallization Conference (AMC), Sept. 26-29, Colorado Springs, CO. (INVITED TUTORIAL)

40. A Probabilistic Framework for Power-Optimal Repeater Insertion for Global Interconnects Under Parameter Variations
    V. Wason and K. Banerjee
    International Symposium on Low Power Electronic Design (ISLPED), San Diego, CA, August 8-10, 2005, pp. 131-136. []
    Nominated for the BEST PAPER AWARD

41. Impact of On-Chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits
    N. Srivastava, X. Qi and K. Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 21-23, 2005, pp. 346-351  []

42. Leakage and Variation Aware Thermal Management of Nanometer Scale ICs
    K. Banerjee, S-C. Lin, and V. Wason
    Proceedings of the IMAPS-Advanced Technology Workshop on Thermal Management, Oct. 25-27, Palo Alto, CA, 2004  []

43. A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies
    N. Srivastava and K. Banerjee
    Proceedings of the 21st International VLSI Multilevel Interconnect Conference (VMIC), Hawaii, Sept. 29-Oct. 2, 2004, pp. 393-398  []

44. Nanometer Scale Interconnect Challenges
    K. Banerjee
    State-Of-The-Art Seminar, 21st International VLSI Multilevel Interconnection Conference (VMIC), Hawaii, Sept. 29-Oct. 2, 2004. (INVITED)  [PDF]

45. A Probabilistic Framework to Estimate Full-Chip Subthreshold Leakage Power Distribution Considering Within-Die and Die-to-Die P-T-V Variations
    S. Zhang, V. Wason and K. Banerjee
    International Symposium on Low Power Electronic Design (ISLPED), Newport Beach, CA, August 9-11, 2004, pp. 156-161  []

46. Simultaneous Optimization of Supply and Threshold Voltages for Low-Power and High-Performance Circuits in the Leakage Dominant Era
    A. Basu, S-C. Lin, V. Wason, A. Mehrotra and K. Banerjee
    ACM Design Automation Conference (DAC), San Diego, CA, June 7-10, 2004, pp. 884-887  []

47. Impact of Off-state Leakage Current on Electromigration Design Rules for Nanometer Scale CMOS Technologies
    S-C. Lin, A. Basu, A. Keshavarzi, V. De and K. Banerjee
    42nd IEEE Annual International Reliability Physics Symposium (IRPS), Phoenix, AZ, April 25-29, 2004, pp. 74-78  []

48. Power Supply Optimization in Sub-130 nm Leakage Dominant Technologies
    Man L Mui, K. Banerjee and A. Mehrotra
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 22-24, 2004, pp. 409-414  []

49. A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array
    A. Basu, S-C. Lin, C. Wasshuber, A. Ionescu and K. Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 22-24, 2004, pp. 259-264  []

50. A Self-Consistent Junction Temperature Estimation Methodology for Nanometer Scale ICs with Implications for Performance and Thermal Management
    K. Banerjee, S-C. Lin, A. Keshavarzi, S. Narendra and V. De
    IEEE International Electron Devices Meeting (IEDM), Washington DC, December 7-10, 2003, pp. 887-890  []

51. SETMOS: A Novel True Hybrid SET-CMOS High Current Coulomb Blockade Oscillation Cell for Future Nano-Scale Analog ICs
    S. Mahapatra, V. Pott, S. Ecoffey, A. Schmid, C. Wasshuber, J. W. Tringe, Y. Leblebici, M. Declercq, K. Banerjee and A. M. Ionescu
    IEEE International Electron Devices Meeting (IEDM), Washington DC, December 7-10, 2003, pp. 703-706  []

52. Nano, Quantum, and Molecular Computing: Are we Ready for the Validation and Test Challenges?
    S. K. Shukla, R. Karri, S. C. Goldstein, F. Brewer, K. Banerjee, and S. Basu
    IEEE International High Level Design Validation and Test Workshop, November 12-14, San Francisco, CA, 2003, pp.3-7. (INVITED PANEL)  []

53. A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
    S. Mahapatra, K. Banerjee, F. Pegeon, and A. M. Ionescu
    IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 9-13, 2003, pp. 497-502  []

54. Nanometer Scale Issues for On-Chip Interconnections
    K. Banerjee
    IUMRS-ICAM, Symposium B-1, Si-LSI-Related Materials, Processes and Characterization Technology, Yokohama, Japan, October 8-13, 2003. (INVITED)  [PDF]

55. Thermal Issues in Designing Nanometer Scale Interconnects
    K. Banerjee
    State-Of-The-Art Seminar, 20th International VLSI Multilevel Interconnection Conference (VMIC), Marina Del Rey, CA, September 22-25, 2003. (INVITED)  [PDF]

56. Modeling of Temperature Dependent Contact Resistance for Analysis of ESD Reliability
    K-H. Oh, J-H. Chun, K. Banerjee, C. Duvvury, and R. W. Dutton
    41st IEEE Annual International Reliability Physics Symposium (IRPS), Dallas, TX, March 30-April 4, 2003, pp. 249-255  []

57. Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs
    A. H. Ajami, K. Banerjee, A. Mehrotra and M. Pedram
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 24-26, 2003, pp. 35-40  []

58. Via Design and Scaling Strategy for Nanometer Scale Interconnect Technologies
    S. Im, K. Banerjee and K. E. Goodson
    Technical Digest IEEE International Electron Devices Meeting (IEDM), San Francisco, December 8-11, 2002, pp. 587-590  []

59. Non-uniform Conduction Induced Reverse Channel Length Dependence of ESD Reliability for Silicided NMOS Transistors
    K-H. Oh, K. Banerjee, C. Duvvury and R. W. Dutton
    Technical Digest IEEE International Electron Devices Meeting (IEDM), San Francisco, December 8-11, 2002, pp. 341-344  []

60. Modeling and Analysis of Power Dissipation in Single Electron Logic
    S. Mahapatra, A. M. Ionescu, K. Banerjee and M. J. Declercq
    Technical Digest IEEE International Electron Devices Meeting (IEDM), San Francisco, December 8-11, 2002, pp. 323-326  []

61. Analysis and Optimization of Substrate Noise Coupling in Single-Chip RF Transceiver Design
    A. Koukab, K. Banerjee, and M. Declercq
    IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 10-14, 2002, pp. 309-316  []

62. Quasi-Analytical Modeling of Drain Current and Conductances of Single Electron Transistors with MIB
    S. Mahapatra, A. M. Ionescu and K. Banerjee
    32nd European Solid-State Device Research Conference (ESSDERC), Florence, Italy, September 24-26, 2002, pp. 391-394  []

63. Power Dissipation Issues in Interconnect Performance Optimization for Sub-180 nm Designs
    K. Banerjee and A. Mehrotra
    IEEE Symposium on VLSI Circuits, Honolulu, HI, June 13-15, 2002, pp. 12-15  []

64. Few Electron Devices: Towards Hybrid CMOS-SET Integrated Circuits
    A. M. Ionescu, M. J. Declercq, S. Mahapatra, K. Banerjee and J. Gautier
    39th ACM Design Automation Conference (DAC), New Orleans, LA, June 10-14, 2002, 88-93. (INVITED)  []

65. A SET Quantizer Circuit Aiming at Digital Communication System
    S. Mahapatra, A. M. Ionescu, K. Banerjee and M. J. Declercq
    IEEE International Symposium on Circuits and Systems (ISCAS), Scottsdale, AZ, May 26-29, 2002, pp. 860-863  []

66. Teaching Microelectronics in the Silicon ICs Showstopper Zone: A Course on Ultimate Devices and Circuits: Towards Quantum Electronics
    A. M. Ionescu, M. J. Declercq, K. Banerjee and S. Mahapatra
    4th European Workshop on Microelectronics Education (EWME), Baiona, Mancomunidad de Vigo, Spain, May 23-24, 2002  []

67. Investigation of Gate to Contact Spacing Effect on ESD Robustness of Salicided Deep Submicron Single Finger NMOS Transistors
    K-H. Oh, C. Duvvury, K. Banerjee and R. W. Dutton
    IEEE Annual International Reliability Physics Symposium (IRPS), Dallas, TX, April 8-11, 2002, pp. 148-155  []

68. Modeling and Analysis of Via Hot Spots and Implications for ULSI Interconnect Reliability
    S. Im, K. Banerjee, and K. E. Goodson
    IEEE Annual International Reliability Physics Symposium (IRPS), Dallas, TX, April 8-11, 2002, pp. 336-345  []

69. Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-Over-Gate-Architecture
    A. M. Ionescu, V. Pott, R. Fritschi, K. Banerjee, M. J. Declercq, Ph. Renaud, C. Hibert, Ph. Fluckiger and G-A. Racine
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 18-20, 2002, pp. 496-501  []

70. Inductance Aware Interconnect Scaling
    K. Banerjee and A. Mehrotra
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 18-20, 2002, pp. 43-47  []

71. 3-D Integrable Optoelectronic Devices for Telecommunications ICs
    P. Dainesi, A.M. Ionescu, L. Thévenaz, K. Banerjee, M. J. Declercq, Ph. Robert, Ph. Renaud, Ph. Fluckiger, C. Hibert and G-A. Racine
    IEEE International Solid State Circuits Conference (ISSCC), February 4-6, San Francisco, 2002, pp. 360-361  []

72. Gate Bias Induced Heating Effect and Implications for the Design of Deep Submicron ESD Protection
    K-H. Oh, C. Duvvury, K. Banerjee and R. W. Dutton
    Technical Digest IEEE International Electron Devices Meeting  (IEDM), Washington, DC, December 3-5, 2001, pp. 315-318  []

73. Localized Heating Effects and Scaling of Sub-0.18 Micron CMOS Devices
    E. Pop, K. Banerjee, P. Sverdrup, R. W. Dutton and K. E. Goodson
    Technical Digest IEEE International Electron Devices Meeting  (IEDM), Washington, DC, December 3-5, 2001, pp. 677-680  []

74. Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion
    A. H. Ajami, K. Banerjee and M. Pedram
    IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 4-8, 2001, pp. 44-48  []

75. Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets
    K. Banerjee and A. Mehrotra
    IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 4-8, 2001, pp. 158-164  []

76. Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects
    T-Y. Chiang, K. Banerjee and K. C. Saraswat
    IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 4-8, 2001, pp. 165-172  []

77. Analysis and Optimization of Distributed ESD Protection Circuits for High-Speed Mixed Signal and RF Applications
    C. Ito, K. Banerjee and R. W. Dutton
    23rd Annual EOS/ESD Symposium, Portland, Oregon, September 9-13, 2001, pp. 355-363  []

78. Interconnect Reliability under ESD Conditions: Physics, Models and Design Guidelines
    K. Banerjee
    23rd Annual EOS/ESD Symposium, Portland, Oregon, September 9-13, 2001, p. 191. (INVITED)  []

79. Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
    A. H. Ajami, K. Banerjee, M. Pedram and L. P.P.P van Ginneken
    38th ACM Design Automation Conference (DAC), Las Vegas, NV, June 18-22, 2001, pp. 567-572  []

80. Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
    K. Banerjee and A. Mehrotra
    38th ACM Design Automation Conference (DAC), Las Vegas, NV, June 18-22, 2001, pp. 798-803. BEST PAPER AWARD  []

81. Accurate Analysis of On-Chip Inductance Effects and Implications for Optimal Repeater Insertion and Technology Scaling
    K. Banerjee and A. Mehrotra
    IEEE Symposium on VLSI Circuits, Kyoto, Japan, June 14-16, 2001, pp. 195-198  []

82. Non-Uniform Chip-Temperature Dependent Signal Integrity
    A. H. Ajami, K. Banerjee and M. Pedram
    IEEE Symposium on VLSI Technology, Kyoto, Japan, June 12-14, 2001, pp. 145-146  []

83. A New Analytical Thermal Model for Multilevel ULSI Interconnects Incorporating Via Effects
    T-Y Chiang, K. Banerjee and K. C. Saraswat
    IEEE International Interconnect Technology Conference (IITC), San Francisco, CA, June 4-6, 2001, pp. 92-94  []

84. RF LDMOS Characterization and Its Compact Modeling
    J. Jang, O. Tornblad, T. Arnborg, Q. Chen, K. Banerjee, Z. Yu and R. W. Dutton
    IEEE/MTT-S International Microwave Symposium, Phoenix, AZ, May 20-25, 2001, pp. 967-970  []

85. 3-D Heterogeneous ICs: A Technology for the Next Decade and Beyond
    K. Banerjee, S. J. Souri, P. Kapur and K. C. Saraswat
    5^th IEEE Workshop on Signal Propagation on Interconnects, Venice, Italy, May 13-16, 2001  []

86. A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance
    Y-C Lu, K. Banerjee, M. Celik and R. W. Dutton
    IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, May 6-9, 2001, pp. 241-244  []

87. Effects of Non-Uniform Substrate Temperature on the Clock Signal Integrity in High Performance Designs
    A. H. Ajami, M. Pedram and K. Banerjee
    IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, May 6-9, 2001, pp. 233-236  []

88. Non-uniform Bipolar Conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design
    K-H. Oh, C. Duvvury, C. Salling, K. Banerjee, and R. W. Dutton
    39th IEEE Annual International Reliability Physics Symposium (IRPS), Orlando, FL, April 30-May 3, 2001, pp. 226-234  []

89. Analysis and Optimization of Thermal Issues in High-Performance VLSI
    K. Banerjee, M. Pedram and A. H. Ajami
    ACM/SIGDA International Symposium on Physical Design (ISPD), Sonoma County, CA, April 1-4, 2001, pp. 230-237. (INVITED)  []

90. Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications
    C. Ito, K. Banerjee, and R. W. Dutton
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 26-28, 2001, pp. 117-122  []

91. Trends for ULSI Interconnections and Their Implications for Thermal, Reliability and Performance Issues
    K. Banerjee
    Seventh International Dielectrics and Conductors for ULSI Multilevel Interconnection Conference (DCMIC), Santa Clara, CA, March 5-9, 2001, pp. 38-50. (INVITED)  []

92. Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs
    S. Im and K. Banerjee
    Technical Digest IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 11-13, 2000, pp. 727-730  []

93. Effect of Via Separation and Low-k Dielectric Materials on the Thermal Characteristics of Cu Interconnects
    T-Y Chiang, K. Banerjee, K. C. Saraswat
    Technical Digest IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 11-13, 2000, pp. 261-264  [