Winter 2015: ECE137A

 

DO NOT GO TO THE SCHEDULED LAB HOURS during the first week of classes. The laboratory/design content of the class is run on an independent basis. Design projects are assigned and a due date is given. Students work in the lab constructing and testing their designs, working in the lab at whatever time they find most suitable to work.

 

Hit the refresh button to make sure you see recent updates to HW, labs, etc

 

Recent updates:

PS #3 has been posted
notes #4,5 have been updated

 

Instructor.. 1

Lectures. 2

Syllabus and Outline.. 2

Exams. 2

Review Sessions. 2

Teaching Assistants. 2

Class Preparation.. 2

Lab Hours and Design Projects. 2

Lab Access During Lab  Periods. 3

Problem Sets: Winter 2015. 3

Picking Up Your Graded Assignments. 4

Homework solutions: 4

Lab Assignments. 4

Textbook.. 5

Lecture Notes. 5

Weekly Reading.. 5

Resources. 6

Old Exams and Solutions. 6

Transistor and IC Datasheets: 6

***********************************************************************

Instructor

Prof. Mark Rodwell

Office Hrs:   Wednesdays 4-5PM, Fridays 11AM-noon, ESB Room 2205F.

Lectures

Tuesdays and Thursday 5PM-615PM   Phelps 3515

Syllabus and Outline

Syllabus  outline

Exams

Midterm exam: Thursday, Feb 5, during lecture time.
Dead week:  March 9-13

Final Exam: Wednesday, March 18, 7:30 - 10:30 p.m.

(from http://registrar.sa.ucsb.edu/cal2015.aspx ,

http://registrar.sa.ucsb.edu/finals-winter.aspx    )

Review Sessions

To cover dates I must travel it is expected that some additional lectures will be scheduled. I will also schedule additional reviews near the times of the later 2 labs, and the mid-term and final exams.  I will be polling the class for suitable times to do this.

 

Date

Time

Location

Subject / Objective

to be announced

6-8PM

Phelps 3515

 

Teaching Assistants

TA

Email

office hours

Location

Maurer, Robert

rmaurer@umail.ucsb.edu

3-4 Friday

The lab !

Rajagopal, Abhejit

abhejit@umail.ucsb.edu

3-4 Tuesday

The lab !

Shen, Yue

yueshen@umail.ucsb.edu

 930-1030 Monday

The lab !

Please note that these office hours will be replaced (will not be held ) during weeks when the TAs are holding office hours in the lab. See below

 

Class Preparation

Comments about class preparation.

Lab Hours and Design Projects

The laboratory/design content of the class is run on an independent basis. Design projects are assigned and a due date is given. Students work in the lab, working in groups of two (not three) constructing and testing their designs, working in the lab at whatever time they find most suitable to work.

 

During the week of that each lab project is due, the above TA hours will *not* be held. 

Instead, the TAs will be in the lab to provide you with guidance in the lab, at hours posted both here and on the lab door.

 

Dates and times when TA hours will be held in  the lab.  Checkoff times=*

Monday

Tuesday

Wednesday

Thursday

Friday

 

 

Jan 21

5-7PM  : RM

Jan 22
7-9PM : AR

Jan 23

5-7PM  : YS

Jan 26
5-7PM: AR 

7-9PM  : RM

Jan 27
6:30-8:30PM: YS

7-10PM: AR 

Jan 28
5-8PM : YS

7-10PM: RM 

Jan 29
*7-9: AR.

*7-9  RM

*7-9: YS

Jan. 30
*5-10PM: AR

*5-10PM:: RM

*5-10PM: :YS

 

 

Feb 11
5-7PM 

Feb 12
6:30-8:30PM 

Feb 13

4-6 PM 

Feb 16

5-7PM 

Feb 17

630-930PM

Feb 18

5-8PM

Feb 19

*6:30-9.30
*6:30-9.30PM 

Feb 20

*5-10PM 

*5-10PM 

March 2

4-6PM

 

March 3

6.30-9.30PM

 

March 4
4-6PM
 

March 5
6.30-8.30PM

 

March 6
4-6 PM

 

March 9

5-7PM

 

March 10
6.30-9.30PM

 

March 11

5-7PM

 

March 12

6.30-9.30PM

 

March 13

*4-10PM  

*4-10PM 
*4-10PM 

 

Lab Access During Lab  Periods

Checkoffs will be in the lab, and will be by appointment. A signup sheet for lab checkoffs will be distributed in lecture. Please see the TAs if you must change your appointment time.   During the checkoff periods, the TAs are not available to provide you with guidance,  and the lab is will be closed except to those checking off.

Problem Sets: Winter 2015

Problem sets are due 5PM in the class homework box in Harold Frank Hall

#

week

what

due

files

1

2

transistor bias circuits

1/14/15

assignment: ece137a_ps1_2015.pdf

updates:

2

3

common-source & common-emitter stages

1/21/15

 

assignment: ece137a_ps2_2015.pdf

updates:

3

4

source/emitter degeneration, common-gate/base stages

1/28/15

assignment: ece137a_ps3_2015.pdf

updates:

4

6

followers, differential stages

2/11/15

assignment: assignment to be posted

updates:

5

7

multi-stage amplifiers

2/18/15

assignment: assignment to be posted

updates:

6

8

multi-stage amplifiers

2/26/15
(Thurs!)

assignment: assignment to be posted

updates:

7

9

multi-stage amplifier, frequency response

3/4/15

assignment: assignment to be posted

updates:

8

10

frequency response, negative feedback

3/11/15

assignment: assignment to be posted

updates:

 

Missing parameters in assignments: Often a problem statement will omit to give certain parameter values. In those cases, use default values, as below.  In some problems, you are asked to use data sheet values for device parameters. In those cases, be certain that the data is not on the data sheet before using these default values.

channel output conductance parameter, lambda (MOSFETS)

0 in DC calculations

1/(10 V) in AC calculations

MOS channel mobility

300 cm^2/(volt-second) NMOS, 200 for PMOS

MOS saturation drift velocity

10^7 cm/s NMOS, 7*10^6 cm/s PMOS

MOS gate length

40 nm

gate oxide thickness

0.8 nm  (SiO2-equivalent: use er=3.8)

MOSFET threshold voltage

+0.3 V (NMOS), -0.3V (PMOS)

Va, Early voltage (BJTs)

100 V.

beta (current gain of BJTs)

100

Vce(sat) (BJTs)

0.5 V

Vbe(on)  (BJTs)

0.7 V

Picking Up Your Graded Assignments

Graded HW and Lab projects are obtained from the TAs. Please see them during either office hours or during their lab hours.

Homework solutions:

Solutions are linked here.

Lab Assignments

Please read the syllabus for procedures. Work in groups of 2 (not 3,4,...,27,...).

#

what

due

files

1

elementary gain stage

design review: 1/23/15
checkoff: 1/29-30/15

report:    2/2/15

lab1_2015.pdf

updates:

2

Multi-stage design

design review: 2/13/15 (1159PM)
checkoff: 2/18-19-20/15

report:    2/23/15

assignment to be posted

lab2_suggestions.pdf



updates:

3

Operational-amplifier design

design review: 3/8/15
checkoff: 3/14/15 only

report:    3/17/15

assignment to be posted

 opamp_comments.pdf

testing_opamps.pdf

updates:

Check-offs are by appointment with the TAs

Guidelines on writing lab reports

Guidelines on building and testing projects

Design review contains: (1) statement of design goals, (2) circuit diagram, (3) calculations proving that the circuit will meet specifications.

Textbook

The main text for the class is the online lecture notes- these are available via the links below.

 

You will also need to have a quality analog IC design text. If you don't have one, the recommended text for this class is  Fundamentals of Microelectronics, by Behzad Razavi.

 

Other high-quality alternatives are  Microelectronic Circuit Design by  R.C. Jaeger and T.N. Blalock, or Analysis and Design of Analog Integrated Circuits, by Grey, Meyer, and Lewis. The Grey/Meyer/Lewis and Razavi texts, are focused and have little added secondary material. These book can be purchased online from many vendors. Older editions have the advantage that used copies can be obtained at a lower price. Any of these books would be just fine.

 

Every textbook covers the material differently, as do the lecture notes. It helps to have several perspectives. 

Lecture Notes

I will be updating these notes this term..

Please read each note set before attending lectures. It will then be much easier to follow the lectures !

week

set

subject

comment

1

1

bipolar transistor DC characteristics

 

1

2

MOSFET DC characteristics

 

1-2

R1

2abc review: small-signal models

study if you have not learned this.

1-2

R2

2abc review: loadline analysis

study if you have not learned this.

2

3

elementary common-emitter amplifier

 

2

4

degeneration, common-source amplifier

 

3

5

source & emitter followers

 

3

6

common-source, common-gate

 

4

7

multi-stage analysis

 

4

8

differential amplifiers, current mirrors

 

5

9

MOS: multi-stage, mirrors, Darlingtons

 

6

10

multi-stage example (bipolar)

 

6

11

MOS multi-stage example

 

7

12

MOS IC process flows. IC design choices

 

7

13

Transistor-level design of op-amps

needs updating

8

14

Fourier transforms

needs updating

9

15

LaPlace transforms

depth of coverage depends on ece2abc

9

16

First-order circuits

depth of coverage depends on ece2abc

10

17

RCL networks, 2nd-order circuits

depth of coverage depends on ece2abc

10

18

other resonant networks.

depth of coverage depends on ece2abc

Weekly Reading

week

Razavi

 

1

chapter 4, 6

 

2

chapter 5,7

 

3

chapter 5,7

 

4

chapter 5,7

 

5

chapter 9

 

6

chapter 10

 

7

chapter 10

 

8

 

 

9

 

 

 

10

 

 

 

Read the text to get a different perspective on the material from the lecture notes.
If your book is not Razavi, look at the notes, and find the similar section in the book.

Resources

material

comment

Transistor amplifier crib sheet

you can bring this to the exams.

High frequency amplifier crib sheet

 

op-amp design tutorial

dated, but seminal

testing operational amplifiers

hints for testing op-amps for design projects

National Semiconductor's Linear Applications Handbook

Dated. Excellent tutorials, many written by the inimitable  Bob Widlar

 

Old Exams and Solutions

year

mid-term

final

2005

exam  solution

 

2006

exam  solution

exam solution

2007

exam  solution

exam  solution

2014

exam  solution

exam  solution

2014

exam  solution

exam  solution

Transistor and IC Datasheets:

Type

link

comment

MOSFETs

 

 

small-signal matched pairs

ALD1101

ALD1102

ALD1105

ALD1106

ALD1107

good for general analog design at moderate frequencies.

small-signal arrays

ALD1116

small-signal array

ALD110800

low (near zero) threshold voltage.

medium-power

VN0104  VP0104

high current devices, good also as small-signal FETs at 1-100mA bias. At lower currents, the data sheet does not provide data, and a curve-tracer must be used

high-power

IRFU014_N-ch

IRFU9014_P-ch

Serve well as a complementary power output stage DC-100kHz.

Bipolar Transistors

 

 

small-signal

2n3904   2n3906

 

medium-power

2N5191 2N5194

 

matched pairs and arrays

THAT300

 

Operational-amplifiers

 

 

5 V op-amps (single-dual, quad)

ALD1702

ALD2702

ALD4702

low-voltage, precision op-amps

3MHz dual-supply op-amp

TL074

 

fast (80MHz) op-amp

AD8031_AD8032