ECE137A Winter 2008
DO NOT GO TO THE SCHEDULED LAB HOURS during the first week of classes. The laboratory/design content of the class is run on an independent basis. Design projects are assigned and a due date is given. Students work in the lab constructing and testing their designs, working in the lab at whatever time they find most suitable to work
Hit the refresh button to make sure you see recent updates to HW, labs, etc
Lab 3: Check off dates:
March 13, and 14, 5-10 PM in lab, BY APPOINMENT WITH TAs. Final design report
due Monday March 17, 9AM in HW box
Week of March
10....TA hours will be held in the lab
Wednesday 6-8 PM Kurtis
Thursday 7-9 PM
Eric
Friday 8-10 PM
John.
Week of March 17....TA hours will be held in the lab
Monday 6-8 PM John
Tuesday 7-9 PM Eric
Wednesday 6-9 PM Eric
Checkoffs and open lab Thursday 5-10 PM
John, 6-10 PM Kurtis
Checkoffs Friday
5-10 PM Erik , 5-10 PM Kurtis, 8-10 John
Sixth Problem set
Problem #2: the load is 5000 Ohms.
TA
Hours and Lab Access During Lab Periods.
Picking
Up Your Graded Assignments
Old
Exam Solutions and Old Exams
small-signal
bipolar transistors:
medium-power bipolar transistors
***********************************************************************
MWF 9-10 AM Psychology 1824.
Class Syllabus: 137aboutline.pdf or Syllabus_ece137A.htm
Rodwell Office Hrs: Mondays, Wednesdays , Fridays: 10-11 AM, Room 2205 Engineering Sciences building.
To cover dates I must travel it is expected that some additional lectures will be scheduled. I will also schedule additional reviews near the times of the later 2 labs, and the mid-term and final exams. I will be polling the class for suitable times to do this.
(these HRS will be replaced during weeks labs are due by TA time in labs)
|
TA |
|
office hours |
Location |
|
Hollar, Kurtis |
Wed. 10-11AM |
TA
trailer (Phelps 1435) |
|
|
Hsieh, Yun-Hao |
Tues
11-12 |
TA
trailer (Phelps 1435) |
|
|
Yan, John |
Mon
12-1 |
TA
trailer (Phelps 1435) |
Please note that these office hours will be replaced (will not be held )
during weeks when the TAs are holding advising office hours in the lab.
Week of March
10....TA hours will be held in the lab
Wednesday 6-8 PM Kurtis
Thursday 7-9 PM
Eric
Friday 8-10 PM
John.
Week of March 17....TA hours will be held in the lab
Monday 6-8 PM John
Tuesday 7-9 PM Eric
Wednesday 6-9 PM Eric
Checkoffs and open lab Thursday 5-10 PM
John, 6-10 PM Kurtis
Checkoffs Friday
5-10 PM Erik , 5-10 PM Kurtis, 8-10 John
During the week of that each lab project is due, the above TA hours will *not* be held.
Instead, the TAs will be in the lab to provide you with guidance in the lab, at hours posted both here and on the lab door.
Checkoffs will be in the lab, and will be by appointment. A signup sheet for
lab checkoffs will be distributed in lecture. Please see the TAs if you must
change your appointment time. During
the checkoff periods, the TAs are not available to provide you with Guidance, and the lab is will be closed except to those
checking off.
Mid term exam: Wed, Feb 6, during lecture time.
Final Exam: Thursday, March 20, 8–11 am
Missing parameters in assignments:
Often a problem statement will omit to give certain parameter values.
In those cases, use default values, as below.
In some problems, you are asked to use data sheet values for device parameters. In those cases, be certain that the data is not on the data sheet before using these default values.
|
lambda (MOSFETS) |
0 in DC calculations 1/(10 V) in AC calculations |
|
MOS channel mobility |
400 cm^2/(volt-second) NMOS, 200 for PMOS |
|
MOS saturation drift velocity |
10^7 cm/s NMOS, 5*10^6 cm/s PMOS |
|
MOS gate length |
90 nm |
|
gate oxide thickness |
1 nm |
|
Va, Early voltage (BJTs) |
100 V. |
|
beta (current gain of BJTs) |
100 |
|
Vce(sat) (BJTs) |
0.5 V |
|
Vbe(on) (BJTs) |
0.7 V |
First Problem Set: ece137a_ps1_2008.pdf
Due Wednesday January 16, 2008, 5 PM, in
HW box
Second problem set : ece137a_ps2_2008.pdf
Due Wednesday January 24, 2008, 5 PM in HW box
Third Problem set: ece137a_ps3_2008.pdf
Due Wednesday January 30 , 2008, 5 PM
in HW box
please note corrections:
Problem 2: The gate width is to be selected so that the device operates with
Vgs 150 mV beyond threshold. Rgen is 100 kOhm and RL is 5 kOhm
Problem 4: power supply voltages are not specified. They are +2 V and -2 V.
Fourth Problem set: ece137a_ps4_2008.pdf
Due Wednesday February 13, 2008, 5 PM
in HW box
Problem #1: supplies are +2 V and -2 V.
Fifth Problem set: ece137a_ps5_2008.pdf
Due Wednesday
February 20, 2008, 5 PM in HW box
Problem #2: Vout is zero volts
Sixth Problem set: ece137a_ps6_2008.pdf
Due Wednesday Febuary 27, 2008, 5 PM
in HW box.
Problem #2: the load is 5000 Ohms.
Seventh Problem Set: ece137a_ps7_2008.pdf
Due Wednesday March 5, 2008, 5 PM in
HW box.
Problem 3: the supplies
are +/- 2 V
Eighth problem set 8: ece137a_ps8_2008.pdf
Due : Wednesday March 12, 2008, 5 PM in
HW box.
Graded HW and Lab projects are obtained from the TAs. Please see them during either office hours or during their lab hours.
a link will be provided here.
Please read the syllabus for procedures. Work in groups of
2; larger groups will not receive credit
.
Guidelines on writing lab reports: writing_lab_reports.pdf
Guidelines on building and testing projects: lab_hints.pdf
ECE137A lab project #1 : ece137a_lab1_2008.pdf
Design review document (ckt diagram and calculations proving that specifications will be met):
due Friday Jan. 25, 5 PM in HW box
Check off dates: Jan 30, 3`, Feb 1, 5-10 PM in lab, BY APPOINMENT WITH TAs.
Final design report due Monday Feb
4, 5 PM in HW box
ECE137A lab project #2: ece137a_lab2_2008.pdf
Design review document (ckt diagram and calculations proving
that specifications will be met): due Wednesday Feb 13,
5 PM in HW box
Check off dates: Feb 20-21-22, 5-10 PM in lab, BY
APPOINMENT WITH TAs.
Final design report due Monday Feb 25, 5 PM in HW box
ECE137A lab project #3: ece137a_lab3_2008.pdf
Check off sheet: lab3_checkout.pdf
Design review document (ckt diagram and calculations proving
that specifications will be met): due Friday
March 7 , 10 PM in HW box
Check off
dates: March 13, and 14, 5-10 PM in lab, BY
APPOINMENT WITH TAs.
Final design report due
Monday March 17, 9AM in HW box
Please download and read the following document regarding testing of the op-amp: testing_opamps_2004.pdf
Good general reference on op-amps.http://www.national.com/an/AN/AN-A.pdf
Key resources, READ THESE: amplifier_gallery.pdf opamp_comments.pdf more_opamp_hints.pdf
The main text for the class is the online lecture notes-
these are available via the links below. Printed copies of the notes will be
available at the Alternative
Copy Shop. You will also need to
have a quality analog IC design text. If you don't have one, recommended texts
would include Grey and Meyer:
Analysis
and Design of Analog Integrated Circuits, Any edition
or Microelectronic Circuit Design, 2nd
edition or 3rd
edition, R.C. Jaeger and T.N. Blalock, or Fundamentals
of Microelectronics, Behzad Razavi
These can be purchased online from many
vendors. Older editions have the advantage that used copies can be obtained at
a lower price. Any of these books would be just fine.
Week 1: Class notes
through set 2.
J&B: Chapter 1 (review of ECE2ABC)
Skim chapter 2 through section 3.8 (review of ECE132)
Read 4.1, 4.2, 4.3 (these should be review from ECE132), 4.4, 4.5, (skip 4.6, skip 4.7), 4.8, 4.9, 4.10
Week 2: Class notes through set 4.
J&B: Read 5.1, 5.2, 5.3 (these should be review from ECE132), (skip 5.4,
skip 5.5), 5.6, 5.7, 5.8, 5.9, 5.10, 5.11,
5.12, 5.13, 10.1-10.5.
Week 3: Class notes through set 6.
J&B: Chapter 13, chapter 14
(skip JFETs)
Week 4: Class Notes through set 8.
J&B: Chapter 15
Week 5: Class Notes through set 10.
J&B: Chapter 16 through 16.5
Week 6: Class Notes
through set 12.
J&B: Remainder of Chapter 16
Week 7: Class Notes through set 13.
Week 8: Class Notes through set 16
Week 9: Class Notes through set 18
Week 10: review !
Transistor amplifier crib sheet new_amplfiiers_2002.pdf
High Frequency Crib sheet HF crib sheet.pdf
Final exams: final_01.pdf final_03.pdf final_04.pdf final_05.pdf final_06.pdf
Mid Term Exams: midterm01.pdf midterm_02.pdf midterm_03.pdf midterm_04.pdf midterm_05.pdf midterm_06.pdf
This is an array of MOSFETs in an IC package. They are hard
to work with.
The data sheet does not distinguish between
source and drain terminals; they are interchangeable, with source and drain
being determined by DC bias. You must
use some imagination to exploit the pre-existing transistor connections IC
within the package. If a transistor you are using has some leads connected