Winter 2023: ECE137A
Last updated 3/10/2023
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recent changes:
Problem set 7 has been posted.
Picking
Up Your Graded Assignments
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Prof. Mark Rodwell
Office Hrs: Mondays,
Fridays 4-5PM, ESB Room 2205F.
Mondays and Wednesdays, 11:00am - 12:15pm, PSYCH 1902
Mid-term Exam: February 8
class period (same room as lecture)
Dead week: March 13-17
Last Lecture: March 16
Final Exam: Thursday, March 23, 12 - 3
p.m. (same room as lecture)
Please see
https://registrar.sa.ucsb.edu/calendars/calendars-deadlines/academic-calendars/academic-calendar-for-2022-2023
, and
https://registrar.sa.ucsb.edu/calendars/calendars-deadlines/final-examinations/winter-final-examination-schedule
There are evening reviews near the times of the 3 labs, and the final exam.
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Date |
Time |
Location |
Subject / Objective |
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Jan 23 |
5-6 PM |
Phelps 1437 |
lab 1 discussion |
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Feb 13 |
5-6 PM |
Phelps 1437 |
lab 2 discussion |
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March 17 Friday |
5-6PM |
Phelps 1437 |
final review |
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TA |
Email |
office hours |
Location |
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Giorgi, Joaquin |
jmgiorgi@umail.ucsb.edu |
Th. 430-530 |
TA trailer. |
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Kabir, Zain |
zkabir@umail.ucsb.edu |
W 5-6 |
TA trailer |
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Nikhar, Srijan |
srijannikhar@ucsb.edu |
M 5-6 |
TA trailer |
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Please note that these office hours
will be replaced (will not be held ) during weeks when the TAs are holding
office hours in the lab. |
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Comments about class preparation.
The laboratory/design content of the class is run on an independent basis. Design projects are assigned and a due date is given. Students work in the lab, working in groups of two (not three) constructing and testing their designs, working in the lab at whatever time they find most suitable to work.
During the week of that each lab project is due, and the week prior to this, the above TA hours will *not* be held. Instead, the TAs will be in the lab to provide you with guidance in the lab, at hours posted both here and on the lab door.
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Dates and times when TA
hours will be held in the lab. Checkoff times=* |
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Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
Sat |
Sun |
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Jan 25 |
Jan 25 |
Jan 27 |
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Jan 30 6-7PM: ZK |
Jan 31 615-715PM:JG 5-6PM:SN
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Feb 1 430-6PM:ZK 615-745PM: JG 6-730:SN |
Feb 2 6-730PM:ZK 430-6PM: JG 7-830PM:SN |
Feb 3 *4-10PM: AA *4-10PM: BB *4-10PM: CC |
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Feb 20: |
Feb 21 5-6PM: JG |
Feb 22 5-6PM: SN |
Feb 23 5-6PM: ZK |
Feb 24 |
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Feb 27 6-7PM: ZK |
Feb 28 615-715PM:JG 5-6PM:SN |
March 1 430-6PM:ZK 615-745PM: JG 6-730:SN |
March 2 6-730PM:ZK 430-6PM: JG 630-8PM:SN |
March 3 checkoffs *4-10PM:ZKK *4-10PM:JG *4-10PM: SN |
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Checkoffs will be in the lab, and will be by appointment. A signup sheet for lab checkoffs will be distributed by the TAs. Please see the TAs if you must change your appointment time. During the checkoff periods, the TAs are not available to provide you with guidance, and the lab is will be closed except to those checking off.
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Problem sets are due 8PM in
the class homework box in Harold Frank Hall |
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# |
week |
what |
due |
files |
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1 |
2 |
transistor bias circuits |
1/18/23 |
assignment: ece137a_ps1_2023.pdf |
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updates: |
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2 |
3 |
common-source &
common-emitter stages |
1/25//23 |
assignment: ece137a_ps2_2023.pdf |
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updates: |
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3 |
4 |
source/emitter
degeneration, common-gate/base stages |
2/1/23 |
assignment: ece137a_ps3_2023.pdf |
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updates: |
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4 |
6 |
followers, differential
stages |
2/15/23 |
assignment: ece137a_ps4_2023.pdf |
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updates: |
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5 |
7 |
multi-stage amplifiers |
2/24/23 |
assignment: ece137a_ps5_2023.pdf |
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updates: |
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6 |
8 |
multi-stage amplifiers |
3/3/23 |
assignment: ece137a_ps6_2023.pdf |
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updates: |
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7 |
9 |
multi-stage amplifier,
frequency response |
3/10/23 |
assignment: ece137a_ps7_2023.pdf |
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updates: |
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8 |
10 |
frequency response,
negative feedback |
not due; recommended study problems |
assignment: ece137a_ps8_2023.pdf |
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updates: |
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Missing parameters in assignments: Often a problem statement will omit to give certain parameter values. In those cases, use default values, as below. In some problems, you are asked to use data sheet values for device parameters. In those cases, be certain that the data is not on the data sheet before using these default values.
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channel output conductance
parameter, lambda (MOSFETS) |
0 in DC calculations 1/(10 V) in AC calculations |
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MOSFET threshold voltage |
+0.3 V (NMOS), -0.3V (PMOS) |
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Va, Early voltage (BJTs) |
100 V. |
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beta (current gain of BJTs) |
100 |
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Vce(sat) (BJTs) |
0.5 V |
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Vbe(on) (BJTs) |
0.7 V |
Graded HW and Lab projects are obtained from the TAs. Please see them during either office hours or during their lab hours.
Solutions will be posted on Gauchospace by the TAs.
Please read the syllabus for procedures. Work in groups of 2 (not 3,4,...,27,..., 42,…).
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# |
what |
due |
files |
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1 |
elementary gain stage |
prelim. report: Jan 27
checkoff: Feb 3 final report: Feb. 6 |
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updates: |
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2 |
Multi-stage design |
prelim report: Feb 24 final report: March 6 |
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updates: |
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3 |
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updates: |
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Check-offs are by
appointment with the TAs |
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Design review contains: (1)
statement of design goals, (2) circuit diagram, (3) calculations proving that
the circuit will meet specifications. |
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The main text for the class is the online lecture notes- these are available via the links below.
You will also need to have a quality analog IC design text. If you don't have one, good choices include Fundamentals of Microelectronics, by Behzad Razavi, Microelectronic Circuit Design by R.C. Jaeger and T.N. Blalock, or Analysis and Design of Analog Integrated Circuits, by Grey, Meyer, and Lewis. These books can be purchased online from many vendors. Older editions have the advantage that used copies can be obtained at a lower price. Any of these books would be just fine.
Every textbook
covers the material differently, as do the lecture notes. It helps to have
several perspectives.
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Please read each note set
before attending lectures. It will then be much easier to follow the lectures
! |
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week |
set |
subject |
comment |
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1 |
bipolar transistor DC
characteristics |
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1 |
MOSFET DC characteristics |
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1-2 |
2abc review: small-signal
models |
study if you have not
learned this. |
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1-2 |
2abc review: loadline
analysis |
study if you have not
learned this. |
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2 |
elementary common-emitter
amplifier |
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2 |
degeneration, common-source
amplifier |
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3 |
source & emitter
followers |
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3 |
common-source, common-gate |
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4 |
multi-stage analysis |
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4 |
differential amplifiers,
current mirrors |
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5 |
MOS: multi-stage, mirrors,
Darlingtons |
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6 |
multi-stage example (bipolar) |
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6 |
MOS multi-stage example |
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7 |
MOS IC process flows. IC
design choices |
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7 |
Transistor-level design of
op-amps |
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8 |
Fourier transforms |
review of 130AB, 10ABC |
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9 |
LaPlace transforms |
review of 130AB, 10ABC |
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9 |
First-order circuits |
review of 130AB, 10ABC |
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10 |
RCL networks, 2nd-order
circuits |
review of 130AB, 10ABC |
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material |
comment |
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you can bring this to the
exams. |
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dated, but seminal |
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hints for testing op-amps
for design projects |
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Dated. Excellent tutorials,
many
written by the inimitable Bob Widlar |
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year |
mid-term |
final |
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2014 |
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2014 |
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2015 |
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2015 |
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2017 |
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2017 |
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2019 |
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2020 |
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2021 |
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2022 |
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Type |
link |
comment |
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MOSFETs |
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small-signal matched pairs |
good for general analog
design at moderate frequencies. |
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small-signal arrays |
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small-signal array |
low (near zero) threshold
voltage. |
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medium-power |
high current devices, good
also as small-signal FETs at 1-100mA bias. At lower currents, the data sheet
does not provide data, and a curve-tracer must be used |
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high-power |
Serve well as a
complementary power output stage DC-100kHz. |
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Bipolar Transistors |
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small-signal |
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medium-power |
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matched pairs and arrays |
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Operational-amplifiers |
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5 V op-amps (single-dual,
quad) |
low-voltage, precision
op-amps |
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3MHz dual-supply op-amp |
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fast (80MHz) op-amp |
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