Sub 20 nm scaling of Si CMOS
faces considerable physical and technological obstacles. It
is imperative to investigate strong potential alternatives.
III-V materials, have high electron mobilities and
offer the potential of surpassing the 22 nm SIA roadmap goals.
Challenges faced in developing III-V devices as an enhancement
to Si CMOS include developing gate insulator with acceptable
surface state density and minimal impact upon mobility, and
growth and integration of into a Si process. Device-level
challenges include the effect of the light electron on vertical
confinement, transconductance, and tunneling, and the impact
of vertical confinement on subthreshold slope and DIBL. Robust
counterparts of Si fabrication processes must be developed
for III-V CMOS.
To address these substantial challenges,
the SRC nonclassical CMOS center has formed a team of expert
researchers in III-V materials, devices and fabrication processes. Research
tasks include development of low-surface-state-density high-K
gate dielectrics, device design and modeling, development of
fabrication process modules and device fabrication and characterization,
and integration of III-V materials onto Silicon |
