Yuan Xie
List of Publications for Evaluation
- 1. Shuangchen Li, Cong Xu, Qiaosha Zou, Jishen Zhao, Yu Lu, and Yuan Xie. 2016. Pinatubo: A Processing-in-memory Architecture for Bulk Bitwise Operations in Emerging Non-Volatile Memories.In Proceedings of the 53rd Annual Design Automation Conference (DAC '16). ACM, New York, NY, USA, Article 173, 6 pages.
- 2. Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, and Yuan Xie. 2016. PRIME: A Novel Processing-in-memory Architecture for NeuralNetworkComputation in ReRAM-based Main Memory. SIGARCH Comput. Archit. News 44, 3 (June 2016), 27-39.
- 3. Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita R. Das, and Yuan Xie. 2016. OSCAR: Orchestrating STT-RAM Cache Traffic for Heterogeneous CPU-GPU Architectures. In The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-49). IEEE Press, Piscataway, NJ, USA, Article 28, 13 pages.
- 4. Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, & Yuan, Xie. (2016). Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 24(10), 3041-3054.
- 5. Dylan Stow, Yuan Xie, Taniya Siddiqua, and Gabriel H. Loh. 2017. Cost-Effective Design of Scalable High-Performance Systems Using Active and Passive Interposers. In Proceedings of the 36th International Conference on Computer-Aided Design (ICCAD '17). IEEE Press, Piscataway, NJ, USA, 728-735.
- 6. Shuangchen Li, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, and Yuan Xie. 2017. DRISA: a DRAM-based Reconfigurable In-Situ Accelerator. In Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-50 '17). ACM, New York, NY, USA, 288-301.