Projects

Analysis and Physical Design for Power-Gating Technique

With continuous shrinking of the minimal feature size, lowering of supply voltages, and lowering of threshold voltages, leakage power is emerging as a major challenge for current and future CMOS designs. Power-gating is an efficient technique for reducing leakage power by shutting off the idle blocks. However, the presence of power-gating may also introduce negative effects on the circuits, which are not considered in the earlier design stages. Ignoring those effects may result in suboptimal designs, and potentially, even nullify the intended power savings. This research targets to address those effects in several physical design stages, including power/ground network design, floorplan, block scheduling, and try to find the optimal solution of those designs when considering the power-gating technique.

Delay Fault Diagnosis for Non-Robust Test

With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that those errors be correctly and quickly diagnosed. The existing delay-fault diagnosis algorithms cannot identify the delay faults that require nonrobust tests, because they ignore non-robust propagation conditions while emulating the failure analyzer’s behavior. We propose a novel approach to perform delay-fault diagnosis for robust and non-robust tests. The experimental results show that our approach can diagnose delay faults with good resolution. It is stable with respect to delay variations that the failure analyzer might experience.

Delay Fault Diagnosis in Presence of Crosstalk for Nanometer Technology

Crosstalk coupling is one of the causes of design timing failures. It is essential that timing failures be correctly and quickly diagnosed. We present a methodology to diagnose the delay-defect in presence of crosstalk, given the physical information such as crosstalk coupling capacitance, neighborhood information and SDF delay information.

Power Aware Physical Design

The advancement in silicon process technologies offer smaller transistors and higher packaging density but suffer from increased power consumption. Several techniques have been deployed in order to lower power consumption and control leakage currents. One of the design techniques applied is power-gating which saves power by turning off inactive blocks which further complicates the analysis and verification of physical power integrity. This research focuses on power verification and optimization solutions for power/ground network with accurate analysis on voltage drop (IR) and electromigration effects when power-gating technique is applied.

The Neighboring Pattern-Insensitive Cell Library Design

In this work we develop the new cell library design style whose delays are insensitive to the surrounding polysilicon patterns.

Modeling the Systematic Layout Pattern-Dependent Delay Variations

In this work we investigate the effect which the surrounding patterns of a polysilicon gate’s channel have on its dimensions, on transistor’s delay, and on leakage current.

A dynamic-logic timing model subject to process-variation effect

After finishing the static CMOS gate timing model considering process variations, all possible noises and multi-input switching cases, we plan to use a similar method to characterize the switching phenomenon in the dynamic logic circuits.

Logic and Layout Synthesis for Engineering Change Orders (ECOs)

ECOs are usually intended to address errors found in the logic during debugging or to facilitate changes made to the design specification to compensate for design problems that are introduced while integrating components of the system design. As a project nears completion, a significant amount of time has already been invested in making the original design efficient and functionally verifiable; therefore, it is important that ECO changes be confined to specific parts of the design, and to have minimal impact on unrelated parts of the design. Recently, due to the dramatic increase in the price of a mask set, a designer may randomly insert spare gates scattering inside a design so that when a re-implementation is required, the new implementation may also be achieved by using spare gates. Our research is focused on addressing changes caused by Engineering Change Orders in logic and layout synthesis methodologies.

Pre-layout Global Net Prediction Techniques

Based on studies performed on numerous placed netlists, we have observed that long nets are not produced randomly by placers, but to some degree are predetermined by the netlist structures. IBM benchmarks run without pre-placed pads produced almost the same set of long nets on different placers. This experiment suggests that long nets can be predicted before placement. Which nets end up long depends on a large extent on netlist structure. Our research is targeted to develop such pre-layout long-wire prediction techniques.