2005
Hailin Jiang, Kai Wang, Malgorzata Marek-Sadowska: Clock skew bounds estimation under power supply and process variations. ACM Great Lakes Symposium on VLSI 2005: 332-336
Qinghua Liu, Malgorzata Marek-Sadowska: A congestion-driven placement framework with local congestion prediction. ACM Great Lakes Symposium on VLSI 2005: 488-493
Chao-Yang Yeh, Malgorzata Marek-Sadowska: Skew-programmable clock design for FPGA and skew-aware placement. FPGA 2005: 33-40
Qinghua Liu, Malgorzata Marek-Sadowska: Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement. ICCD 2005: 31-37
Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif: Benefits and Costs of Power-Gating Technique. ICCD 2005: 559-566
Qinghua Liu, Malgorzata Marek-Sadowska: Wire length prediction-based technology mapping and fanout optimization. ISPD 2005: 145-151
Bo Hu, Yue Zeng, Malgorzata Marek-Sadowska: mFAR: fixed-points-addition-based VLSI placement algorithm. ISPD 2005: 239-241
Chung-Kuan Tsai, Malgorzata Marek-Sadowska: An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis. ISQED 2005: 654-661
2004
Kai Wang, Malgorzata Marek-Sadowska: Buffer sizing for clock power minimization subject to general skew constraints. DAC 2004: 159-164
Yajun Ran, Malgorzata Marek-Sadowska: On designing via-configurable cell blocks for regular fabrics. DAC 2004: 198-203
Qinghua Liu, Malgorzata Marek-Sadowska: Pre-layout wire length and congestion estimation. DAC 2004: 582-587
Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska: Eliminating False Positives in Crosstalk Noise Analysis. DATE 2004: 1192-1197
Bo Hu, Malgorzata Marek-Sadowska: Multilevel expansion-based VLSI placement with blockages. ICCAD 2004: 558-564
Yajun Ran, Malgorzata Marek-Sadowska: An integrated design flow for a via-configurable gate array. ICCAD 2004: 582-589
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Diagnosis of Hold Time Defects. ICCD 2004: 192-199
Kai Wang, Malgorzata Marek-Sadowska: Potential Slack Budgeting with Clock Skew Optimization. ICCD 2004: 265-271
Yajun Ran, Malgorzata Marek-Sadowska: The Magic of a Via-Configurable Regular Fabric. ICCD 2004: 338-343
Kai Wang, Malgorzata Marek-Sadowska: Clock network sizing via sequential linear programming with time-domain analysis. ISPD 2004: 182-189
Qinghua Liu, Malgorzata Marek-Sadowska: A study of netlist structure and placement efficiency. ISPD 2004: 198-203
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Delay Fault Diagnosis Using Timing Information. ISQED 2004: 485-490
Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska: Pipelining Sequential Circuits with Wave Steering. IEEE Trans. Computers 53(9): 1205-1210 (2004)
2003
Kai Wang, Malgorzata Marek-Sadowska: On-chip power supply network optimization using multigrid-based technique. DAC 2003: 113-118
Chao-Yang Yeh, Malgorzata Marek-Sadowska: Delay budgeting in sequential circuit with application on FPGA placement. DAC 2003: 202-207
Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska: Gain-based technology mapping for discrete-size cell libraries. DAC 2003: 574-579
Bo Hu, Malgorzata Marek-Sadowska: Wire length prediction based clustering and its application in placement. DAC 2003: 800-805
Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska: Temporofunctional crosstalk noise analysis. DAC 2003: 860-863
Yajun Ran, Malgorzata Marek-Sadowska: Crosstalk noise in FPGAs. DAC 2003: 944-949
Kai Wang, Malgorzata Marek-Sadowska: Power/Ground Mesh Area Optimization Using Multigrid-Based Technique. DATE 2003: 10850-10855
Chao-Yang Yeh, Malgorzata Marek-Sadowska: Minimum-Area Sequential Budgeting for FPGA. ICCAD 2003: 813-817
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Multiple Fault Diagnosis Using n-Detection Tests. ICCD 2003: 198-
Bo Hu, Hailin Jiang, Qinghua Liu, Malgorzata Marek-Sadowska: Synthesis and placement flow for gain-based programmable regular fabrics. ISPD 2003: 197-203
Bo Hu, Malgorzata Marek-Sadowska: Fine granularity clustering for large scale placement problems. ISPD 2003: 67-74
Chung-Kuan Tsai, Malgorzata Marek-Sadowska: Modeling Crosstalk Induced Delay. ISQED 2003: 189-194
Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen: Minimizing Inter-Clock Coupling Jitter. ISQED 2003: 333-338
Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski: An Efficient and Effective Methodology on the Multiple Fault Diagnosis. ITC 2003: 329-338
Chao-Yang Yeh, Malgorzata Marek-Sadowska: Sequential delay budgeting with interconnect prediction. SLIP 2003: 23-30
Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska: Wire length prediction in constraint driven placement. SLIP 2003: 99-105
Arindam Mukherjee, Malgorzata Marek-Sadowska: Clock and Power Gating with Timing Closure. IEEE Design & Test of Computers 20(3): 32-39 (2003)
2002
Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer: Coping with buffer delay change due to power and ground noise. DAC 2002: 860-865
Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska: Sizing Power/Ground Meshes for Clocking and Computing Circuit Components. DATE 2002: 176-185
Lauren Hui Chen, Malgorzata Marek-Sadowska: Closed-Form Crosstalk Noise Metrics for Physical Design Applications. DATE 2002: 812-819
Amit Singh, Malgorzata Marek-Sadowska: Efficient circuit clustering for area and power reduction in FPGAs. FPGA 2002: 59-66
Bo Hu, Malgorzata Marek-Sadowska: Congestion minimization during placement without estimation. ICCAD 2002: 739-745
Chih-Wei Jim Chang, Malgorzata Marek-Sadowska: ATPG-based logic synthesis: an overview. ICCAD 2002: 786-789
Lauren Hui Chen, Malgorzata Marek-Sadowska: Incremental delay change due to crosstalk noise. ISPD 2002: 120-125
Bo Hu, Malgorzata Marek-Sadowska: FAR: fixed-points addition & relaxation based placement. ISPD 2002: 161-166
Lauren Hui Chen, Malgorzata Marek-Sadowska: Efficient Closed-Form Crosstalk Delay Metrics. ISQED 2002: 431-436
Amit Singh, Malgorzata Marek-Sadowska: FPGA interconnect planning. SLIP 2002: 23-30
Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska: Efficient circuit clustering for area and power reduction in FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 643-663 (2002)
2001
Chih-Wei Jim Chang, Malgorzata Marek-Sadowska: Who are the alternative wires in your neighborhood? (alternative wires identification without search). ACM Great Lakes Symposium on VLSI 2001: 103-108
Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska: Latency and Latch Count Minimization in Wave Steered Circuits. DAC 2001: 383-388
Tong Xiao, Malgorzata Marek-Sadowska: Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification. DAC 2001: 653-656
Chih-Wei Chang, Kai Wang, Malgorzata Marek-Sadowska: Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques. DAC 2001: 97-102
Chih-Wei Chang, Bo Hu, Malgorzata Marek-Sadowska: In-place delay constrained power optimization using functional symmetries. DATE 2001: 377-382
Nobuo Funabiki, Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska: A Global Routing Technique for Wave-Steering Design Methodology. DSD 2001: 430-437
Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska: Interconnect pipelining in a throughput-intensive FPGA architecture. FPGA 2001: 153-160
Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska: Interconnect Resource-Aware Placement for Hierarchical FPGAs. ICCAD 2001: 132-136
Chih-Wei Chang, Malgorzata Marek-Sadowska: Single-Pass Redundancy Addition and Removal. ICCAD 2001: 606-609
Tong Xiao, Malgorzata Marek-Sadowska: Gate Sizing to Eliminate Crosstalk Induced Timing Violation. ICCD 2001: 186-191
Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee, Amit Singh: Interconnect complexity-aware FPGA placement using Rent's rule. SLIP 2001: 115-121
2000
Chih-Wei Chang, Chung-Kuan Cheng, Peter R. Suaris, Malgorzata Marek-Sadowska: Fast post-placement rewiring using easily detectable functional symmetries. DAC 2000: 286-289
Luca Macchiarulo, Malgorzata Marek-Sadowska: Wave-steering one-hot encoded FSMs. DAC 2000: 357-360
Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska: Wave Steered FSMs. DATE 2000: 270-276
Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska: A novel high throughput reconfigurable FPGA architecture. FPGA 2000: 22-29
Tong Xiao, Malgorzata Marek-Sadowska: Worst Delay Estimation in Crosstalk Aware Static Timing Analysis. ICCD 2000: 115-120
Lauren Hui Chen, Malgorzata Marek-Sadowska: Aggressor alignment for worst-case coupling noise. ISPD 2000: 48-54
Tong Xiao, Malgorzata Marek-Sadowska: Efficient Delay Calculation in Presence of Crosstalk. ISQED 2000: 491-498
Yu-Liang Wu, Hongbing Fan, Malgorzata Marek-Sadowska, C. K. Wong: OBDD Minimization Based on Two-Level Representation of Boolean Functions. IEEE Trans. Computers 49(12): 1371-1379 (2000)
1999
Tong Xiao, Malgorzata Marek-Sadowska: Crosstalk Reduction by Transistor Sizing. ASP-DAC 1999: 137-140
Arindam Mukherjee, Ranganathan Sudhakar, Malgorzata Marek-Sadowska, Stephen I. Long: Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique. DAC 1999: 466-471
Amit Singh, Malgorzata Marek-Sadowska: Circuit clustering using graph coloring. ISPD 1999: 164-169
Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska: STAR-ATPG: a high speed test pattern generator for large scan designs. ITC 1999: 1021-1030
Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang: Modeling Crosstalk in Resistive VLSI Interconnections. VLSI Design 1999: 470-475
Douglas Chang, Malgorzata Marek-Sadowska: Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs. IEEE Trans. Computers 48(6): 565-578 (1999)
Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska: Circuit Optimization by Rewiring. IEEE Trans. Computers 48(9): 962-970 (1999)
1998
Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee: Functional Scan Chain Testing. DATE 1998: 278-
Douglas Chang, Malgorzata Marek-Sadowska: Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs. FPGA 1998: 161-167
1997
Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng: A Test Synthesis Approach to Reducing BALLAST DFT Overhead. DAC 1997: 466-471
Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska: STARBIST: Scan Autocorrelated Random Pattern Generation. DAC 1997: 472-477
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska: Post-Layout Logic Restructuring for Performance Optimization. DAC 1997: 662-665
Douglas Chang, Malgorzata Marek-Sadowska: Buffer Minimization and Time-Multiplexed I/O on Dynamically Reconfigurable FPGAs. FPGA 1997: 142-148
Marek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang: Decomposition of Multiple-Valued Relations . ISMVL 1997: 13-18
Stan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak: Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. ISMVL 1997: 287-292
Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski: Scan-Encoded Test Pattern Generation for BIST. ITC 1997: 548-556
Chien-Chung Tsai, Malgorzata Marek-Sadowska: Boolean Functions Classification via Fixed Polarity Reed-Muller Forms. IEEE Trans. Computers 46(2): 173-186 (1997)
1996
Chien-Chung Tsai, Malgorzata Marek-Sadowska: Multilevel Logic Synthesis for Arithmetic Functions. DAC 1996: 242-247
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee: Test Point Insertion: Scan Paths through Combinational Logic. DAC 1996: 268-273
David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska: A New Hybrid Methodology for Power Estimation. DAC 1996: 439-444
Chien-Chung Tsai, Malgorzata Marek-Sadowska: Logic Synthesis for Testability. Great Lakes Symposium on VLSI 1996: 118-121
Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska: Fast Boolean optimization by rewiring. ICCAD 1996: 262-269
Ashok Vittal, Hein Ha, Forrest Brewer, Malgorzata Marek-Sadowska: Clock skew optimization for ground bounce control. ICCAD 1996: 395-399
Chien-Chung Tsai, Malgorzata Marek-Sadowska: Generalized Reed-Muller Forms as a Tool to Detect Symmetries. IEEE Trans. Computers 45(1): 33-40 (1996)
1995
Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen: Logic rectification and synthesis for engineering change. ASP-DAC 1995
Yu-Liang Wu, Malgorzata Marek-Sadowska: Routing on regular segmented 2-D FPGAs. ASP-DAC 1995
Ashok Vittal, Malgorzata Marek-Sadowska: Power Optimal Buffered Clock Tree Design. DAC 1995: 497-502
Ashok Vittal, Malgorzata Marek-Sadowska: Power Distribution Topology Design. DAC 1995: 503-507
Yu-Liang Wu, Malgorzata Marek-Sadowska: Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing. DAC 1995: 568-573
Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng: Logic Synthesis for Engineering Change. DAC 1995: 647-652
Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng: An Efficient Algorithm for Local Don't Care Sets Calculation. DAC 1995: 663-667
1994
Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska: Layout Driven Logic Synthesis for FPGAs. DAC 1994: 308-313
Chien-Chung Tsai, Malgorzata Marek-Sadowska: Boolean Matching Using Generalized Reed-Muller Forms. DAC 1994: 339-344
Ashok Vittal, Malgorzata Marek-Sadowska: Minimal Delay Interconnect Design Using Alphabetic Trees. DAC 1994: 392-396
Yu-Liang Wu, Malgorzata Marek-Sadowska: An Efficient Router for 2-D Field Programmable Gate Arrays. EDAC-ETC-EUROASIC 1994: 412-416
Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska: Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. EDAC-ETC-EUROASIC 1994: 620-624
Chien-Chung Tsai, Malgorzata Marek-Sadowska: Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms. ISCAS 1994: 287-290
1992
Shih-Chieh Chang, Malgorzata Marek-Sadowska: Technology Mapping via Transformations of Function Graphs. ICCD 1992: 159-162
1991
Malgorzata Marek-Sadowska, Majid Sarrafzadeh: The Crossing Distribution Problem. ICCAD 1991: 528-531
1990
Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh: Delay and Area Optimization in Standard-Cell Design. DAC 1990: 349-352
Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh: Floorplanning with Pin Assignment. ICCAD 1990: 98-101
1989
Rajiv Dutta, Malgorzata Marek-Sadowska: Automatic Sizing of Power/Ground (P/G) Networks in VLSI. DAC 1989: 783-786
Fillia Makedon, Malgorzata Marek-Sadowska: Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic. ICCAL 1989: 359-378