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http://www.ece.ucsb.edu/courses/ECE124/124A_F11Banerjee/ | http://TinyURL.com/124A-F11
Course Info | Syllabus | Lecture
Notes& Refs | HW& Keys | Projects | Resources
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- ECE 124A - Very-Large-Scale
Integration Principles
UCSB,
ECE, Fall 2011
- Instructor: Prof. Kaustav Banerjee
kaustav
(at) ece.ucsb.edu
Office: Harold
Frank Hall (HFH) 4151
Phone:
(805) 893-3337 Fax: (805) 893-3262
- Teaching Assistant: Jiahao Kang
jiahao_kang (at)
ece.ucsb.edu
Office: HFH
2152C
- Lecture Location
: ESB 1003
- Lecture Time: Tue.
& Thu. 3:30PM-4:45PM
- Lab Location: ECI Cooper Lab (HFH
1140)
- Lab Time: Mon.
6:00PM-8:50PM
- It is also TA office hour
- More info
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Textbook
CMOS VLSI
DESIGN
4th
Edition
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- Course
Description
- Midterm: Tuesday, Nov 8, 2011
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- Lecture Notes:
| - Lecture 1,
09/22/11 |
- Lecture 2,
09/27/11 |
- Lecture 3, 09/29/11 |
| - Lecture 4,
10/04/11 |
- Lecture 5,
10/06/11 |
- Lecture 6, 10/11/11 |
| - Lecture 7,
10/13/11 |
- Lecture 8,
10/18/11 |
- Lecture 9, 10/20,11 |
| - Lecture 10,
10/25/11 |
- Lecture 11,
10/27/11 |
- Lecture 12, 11/01/11 |
| - Lecture 13,
11/03/11 |
- Lecture 14,
11/10/11 |
- Lecture 15, 11/15/11 |
| - Lecture 16,
11/17/11 |
- Lecture 17,
11/22/11 |
- Lecture 18,
12/01/11 |
- References:
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G.
E. Moore, "Cramming more components onto integrated circuits,"
Electronics Magazine, pp. 114-117, 1965.
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S. Borkar,
"Design Challenges of Technology Scaling," IEEE Micro, pp.
23-29, 1999.
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X. Zhou,
"Threshold voltage definition and extraction for
deep-submicron MOSFETs", Sol. Stat. Elec.,
2001
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S. C.
Lin, "Cool Chips: Opportunities and Implications for Power and
Thermal Management", IEEE TED, 2008
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K. Banerjee, "A Power-Optimal Repeater Insertion
Methodology for Global Interconnects in Nanometer Designs",
IEEE TED, 2002
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Intel, "From Sand to Silicon"
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Intel, "From Sand to
Circuit" |
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S. H. Rasouli, "Design Optimization of FinFET Domino
Logic Considering the Width Quantization Property", IEEE TED,
2010
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K. Banerjee, "3-D ICs: A Novel Chip Design for
Improving Deep-Submicrometer Interconnect Performance and
Systems-on-Chip Integration", PROCEEDINGS OF THE IEEE,
2001
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K.
Banerjee, "Analysis of On-Chip Inductance Effects for
Distributed RLC Interconnects", IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems,
2012
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- Do NOT copy from each other!
- Homework Box: HFH 3120, Row 2 Col 3
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- Course projects: LVS 64-bit Adder
- Reference Hint
- Due before the final. You are
required to hand in a project report.
- Work either individually or in a
group of maximum two.
- Each student in a group will be orally examined by the TA.
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Midterm 2010 | Solutions
-
Midterm + solutions 2011
- In this course you will need to use these software: (Manuals provided)
- Warning:
Please do NOT print copies of these manuals!
- IMPORTANT: To set up the environment for
your lab:
- 1, log on to linux.engr.ucsb.edu by SSH
- 2, put startup file in your
user folder and start a shell with the command:
Bourne Again
SHell: .bashrc with bash
command;
C shell: .cshrc with csh command.
- Then type hspice,
cscope, max or sue to start a software.
- For
detail, see Environment Setup Guidance
.
- Files for
HW:
-
For HW1: inv.sp
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MOS Model Libraries used in HSpice Simulation: http://ptm.asu.edu/
- HSpice Netlist
Example for HWs
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