References:
Cramming more
Components onto Integrated Circuits, by Gordon E. Moore
S. Borkar, "Design Challenges of Technology Scaling," IEEE Micro, vol. 19, pp. 23-29, Jul-Aug 1999. S. Lin, et. al.,"Analysis and Implications of IC Cooling for Deep Nanometer Scale CMOS Technologies," IEDM, 2005. K.
Banerjee, A. Mehrotra,"A Power-Optimal Repeater Insertion Methodology
for Global Interconnects in Nanometer Designs," IEEE TRANSACTIONS ON
ELECTRON DEVICES, vol. 49, pp. 2001-2007, November 2002.Hamed
Dadgou, Rajiv V. Joshi, K. Banerjee,"A Novel Variation-Aware Low-Power
Keeper Architecture for Wide Fan-in Dynamic Gates," DAC, 2006.Lectures: