LECTURE NOTES AND REFERENCES

 

Lecture 1

Lecture Note

 

Lecture 1

Lecture Note.

 

Lecture 1

Lecture Note.

 

Lecture 1

Lecture Note.

References:

  1.  W. C. Elmore, “The transient response of damped linear networks with Particular Regard to Wideband Amplifiers” J. Appl. Phys., vol. 19, pp. 55–63, Jan. 1948. [PDF]  

  2.  K. Banerjee et al., "3-D ICs: A novel chip design for improving deep submicron interconnect performance and systems-on-chip integration," Proceedings of the IEEE, Vol. 89, No. 5, pp. 602-633, 2001. [PDF]  

  3. K. Nabors and J. White, “FastCap: a multipole accelerated 3-D capacitance extraction program,” IEEE TCAD, vol. 10, no. 11, pp.
    1447–1459, Nov. 1991. [PDF]

  4. A. E. Ruehli, “Inductance calculations in a complex integrated circuit environment,” IBM J. Res. Develop., pp. 470–481, Sept. 1972. [PDF]

  5. M. Kamon et al., “FASTHENRY: A multipole-accelerated 3-D inductance extraction program,” IEEE Trans. Microwave Theory & Techniques., vol. 42, pp. 1750–1758, Sept. 1994. [PDF]

  6. A. Deutsch, et al., “When are transmission-line effects important for on-chip interconnections?,” IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1836–1846, Oct. 1997. [PDF]

  7. R. Suaya et al., "Modeling and extraction of nanometer scale interconnects: challenges and opportunities," Proceedings of the 23rd
    Advanced Metallization Conf. 2006. [PDF]

     

 

Lecture 1

Lecture Note.

References:

  1.  K. Banerjee and A. Mehrotra, "Global (Interconnect) Warming," IEEE Circuits and Devices Magazine, pp. 16-32, 2001. [PDF]  

  2.  K. Banerjee and A. Mehrotra, "A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs," IEEE Transactions on Electron Devices, Vol. 49, No. 11, pp. 2001-2007, 2002. [PDF]  
     

 

Lecture 1

Lecture Note.

References:

  1. K. Banerjee and A. Mehrotra, "Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 8, pp. 904-915, 2002.  [PDF]  

  2. A. H. Ajami, K. Banerjee and M. Pedram, "Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI," International Journal of Analog Integrated Circuits and Signal Processing, Vol. 42, No. 3, pp. 277-290, 2005.  [PDF]  

  3. V. Wason and K. Banerjee, "  A Probabilistic Framework for Power-Optimal Repeater Insertion for Global Interconnects Under Parameter Variations," IEEE International Symposium on Low Power Electronic Design, 2005, pp. 131-136.  [PDF]  

  4. A. H. Ajami, K. Banerjee and M. Pedram, "Modeling and Analysis of Non-Uniform Substrate Temperature Effects on Global ULSI Interconnects,"IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, pp. 849-861, 2005. [PDF]  
     

Lecture 1

Lecture Note.

References:

  1.  K. Banerjee, S. Im and N. Srivastava, "Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond," Proc. Advanced Metallization Conf., 2005. [PDF]  

  2. S. Suaya, et al., "Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities," Proc. Advanced Metallization Conf., 2006. [PDF]  

  3. A. M. Niknejad and R. G. Meyer, "Analysis of Eddy-current Losses Over Conductive Substrates with Applications to Monolithic Inductors and Transformer" IEEE Trans. on Microwave Theory and Techniques, 2001.  [PDF]  

  4. K. Banerjee and N. Srivastav, "Are Carbon Nanotubes the Future of VLSI Interconnects?" IEEE/ACM Design Automation Conference (DAC), 2006, pp. 809-814. [PDF]  

 

 

Lecture 1

Lecture Note.

References:

  1. T. Sakurai and A R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," IEEE d. of Solid State Circuits, Vol. 25, No. 2, pp. 584-594, Apr. 1990. [PDF]  

  2. K. Roy, S. Mukhopadhay, H. Mahmoodi-Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits", in Proc. of the IEEE, Vol. 91, No. 2, Februray 2003 pp 305 -- 327.  [PDF]  

  3. T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. P. Wong, F. Beouff, “The End of CMOS Scaling,” invited paper, IEEE Circuits and Devices Magazine, pp. 16 – 26, 2005.  [PDF]  

  4. S. Thompson, P. Packan, and M. Bohr, “MOS scaling: Transistor challenges for the 21st century,” Intel Technol. J., vol. Q3, 1998. [PDF]  

 

Lecture 1

Lecture Note.

References:

  1. Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee, "A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model," IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3342-3350, 2007. [PDF]  

  2. Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee, "A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Electrothermal Couplings and Full-Chip Package Thermal Model," IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3351-3360, 2007.  [PDF]  

  3. S-C. Lin, N. Srivastava and K. Banerjee, “A Thermally Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs,” International Conference on Computer Design (ICCD), San Jose, October 2-5, 2005, pp. 411-416.  [PDF]  

 

Lecture 1

Lecture Note.

References:

  1. Sheng-Chih Lin and Kaustav Banerjee, "Cool Chips: Opportunities and Implications for Power and Thermal Management" IEEE Transactions on Electron Devices, Vol. 55, No. 1, pp. 245-255, 2008. [PDF]  

Lecture 1

    Project Discussions

 

Lecture 1

Lecture Note.

References:

  1. E.G. Friedman, "Clock distribution networks in synchronous digital integrated circuits," Proc. IEEE, vol.89, no.5, pp.665–692, May 2001. [PDF]  

  2. K. Bowman, S. Duvall, and J. Meindl, "Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration," IEEE JSSC, pp. 183--190, Feb. 2002. [PDF]  

Lecture 1

Lecture Note.

References:

  1. H. F. Dadgour, R. V. Joshi and K. Banerjee , "A Novel Variation-Aware Low-Power Keeper Architecture for Wide Fan-in Dynamic Gates," ACM Design Automation Conference (DAC), San Francisco, California, July 24-28, 2006, pp. 977-982. [PDF]  

 

Lecture 14

Lecture Note.

References:

  1. R. W. Mann et al. , "Ultralow-power SRAM technology," IBM J. RES. & DEV. VOL. 47 NO. 5/6 SEPTEMBER/NOVEMBER 2003. [PDF]  

  2. J. A. Mandelman et al. , "Challenges and future directions for the scaling of dynamic random-access memory (DRAM)," IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002.  [PDF]

 

Lecture 15

Lecture Note.

References:

  1. H. F. Dadgour and K. Banerjee  , "Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications ," ACM Design Automation Conference (DAC), San Diego, CA, June 4-8, 2007. [PDF]  

 

Lecture 15

Lecture Note.

 

 

 

 

 

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