ECE 152A - Winter 2006

University of California, Santa Barbara
Department of Electrical and Computer Engineering

Digital Design Principles

ECE 152A - Summer 2008

Prof. Volkan Rodoplu

Lectures: Monday/Wednesday 12:30 - 1:50 pm at Rm 3361, Engineering II Building.

Professor's Office hours: TBA

in Room 4113, Harold Frank Hall; starting June 30, 2008.

Syllabus

Midterm Exam: in class, see course calendar in Syllabus

Final Exam: In class, in Parts I and II, in the last week of courses. (See course calendar in syllabus.)

Announcements

09/01/08: Final grades have been posted on GOLD.

08/21/08: HW #3 : You can collect your HW3 in Digilab today between 4:00 and 5:00 pm or tomorrow (Aug 22, 2008) between 1:30 and 2:30 pm. If you cannot make it to either of these slots, then email your TA to find out when and where you can get back your home works.

08/19/08: HW #3 Solution has been updated to include solution for CR #17.
08/18/08: Mid-term solutions are now online.

08/14/08: HW #4: For HW4, solve the problem #3 from HW5 (CR Problem 32) also.

08/08/08: Lab # 4: We will allow students a "late check-out" but at 50% penalty.
This penalty applies to every part (separately) that is late. (It does not apply to the parts that are on time.) The latest time to show your check-out to your TA is Friday, August 15, 12:00 PM, and must be arranged with your own TA.

08/04/08: HW #3, CR Problem 22: For the Moore machine, it is OK to draw ONLY the state table. (The state diagram gets complicated.)

08/04/08: HW #3, CR Problem 17, Explanation: In this problem, an up-counter is a counter that counts in the upward direction. The CLR input clears the counter, that is, it sets the count to 0. The LOAD input loads the external value [L_B L_A] into the counter. The COUNT instructs the counter to count. The precedence of these is as described in the problem statement. When all three control inputs are 0, the counter holds its current value.

07/29/08: Lab #4 the Sample-Testbench and Sample C program have been updated.
07/15/08: Lab #3 problem set is due during the week of Lab3 checkout (on 07/28 or 07/29). However we strongly encourage you to submit it to the TAs during your lab sessions next week (on 07/21 or 07/22).
07/15/08: Please attend your own lab sessions for Pre-lab submission and Check-outs. It has been found that some students switch lab sessions without the prior consent of the TAs. Prof. Rodoplu discourages this practice and has asked the TAs not to help the students if they are found doing so.
06/23/08 : For HW #1, Problem # 8 of the Course Reader: If you have found the minimum SOP expression for each of the outputs of this circuit, and yet your implementation uses more than 11 gates, this is fine. We will give you full credit.

06/23/08: THE HOMEWORK BOX is on the 3rd floor of Harold Frank Hall. Please locate the homework box so that you know where to hand in your assignment.

06/23/08: Please read the UCSB/ECE FPGA Board web page: http://vader.ece.ucsb.edu/digilab-fpga/

06/23/08: For Lab # 1: Please note that NOT all TTL parts are available. See the hyperlink below on ECE Shop: List of Available Parts (under Lab Handouts). Only these chips are available in the lab, so plan your TTL implementation accordingly.

06/23/08: Please use TTL (7400 series) for your labs (not CMOS 4000 series parts!).

06/23/08: For the pre-labs, you need to hand in only 1 solution per team (put both team members' names on your solutions.).

06/23/08: Check in the ECE Shop (Room: 1160, Harold Frank Hall; M-F: 8:00-12:00 and 1:00-4:00) to get the access cards for the Digital lab.

Course Reader

(Homework is assigned from the reader.)

CourseReader_Problems 10 to 14

CourseReader Problems 18

CourseReader Problems 19-20

CourseReader Problems 32-33

Homework - Solutions

The homework is due in the ECE 152A Homework Box on the 3rd floor of Harold Frank Hall.

(After you exit the elevator, go straight through the double doors across from you. The homework box is outside after you go through the double doors.)

HW # 1

(due July 11, 2008, Friday, 2:00 PM)

For HW # 1, PLEASE SKIP PROBLEM # 6.

DO THE REST OF THE PROBLEMS.

HW # 2

(due July 25, 2008; 2:00 PM)

For HW # 2: PLEASE SKIP PROBLEMS 3, AND 9. (These are B & V Problem 7.32, and Problem # 16 in Course Reader).

DO THE REST OF THE PROBLEMS.

HW # 3

(You are given 3 weeks to complete this long homework. Start early! Make some progress every week)

(due August 15, 2008, 2:00 PM)

For HW # 3: PLEASE SKIP PROBLEMS 1-3 (the B&V textbook problems). Do the REST of the Problems, which are from the Course Reader.

HW # 4

(due August 22, 2008, 2:00 PM)

For HW # 4: PLEASE solve Problem # 3 from HW # 5 also.

There is no HW # 5 this quarter due to the fact that the Summer Quarter is a shorter quarter.

Grading Guidelines for Homeworks and Labs

Lab Handouts
Lab Schedule

Print out Data Sheets for each lab

ECE Shop: List of Available Parts

UCSB/ECE DigiLab FPGA Board Information

ALL PRE-LABS DUE ARE AT THE BEGINNING OF YOUR LAB.

THE CHECK-OUTS FOR DEMOS MUST BE DONE WITHIN FIRST 1 HR. OF THE LAB SECTION.

*** All the lab dates below are for "week of" the date indicated,

at the beginning of your lab section **.

Lab #1

Nothing is due: June 30, 2008 (but highly encouraged to complete as much of Steps # 1 and # 2 as possible.)

Pre-lab due: (Steps # 1 and # 2 due) July 7, 2008. [Demo of Steps # 3 and/or # 4 encouraged, but not required.]

Check-out (Steps # 3 and # 4): July 14, 2008

Lab #2

Pre-lab due: July 14, 2008 [This is a long pre-lab; start early!]

Check-out: July 21, 2008

Lab #3

Lab starts: July 21, 2008

Check-out: July 28, 2008

(Hint: Use teamwork to manage the wiring to get it done by the deadline.)

Lab # 4 Lab-4 help Sample C program cbw.h cbw32bc.lib lab4_verilog Sample-Testbench cbw32.dll

Lab starts: July 28, 2008

(There is no pre-lab for this lab.)

Part 1 due: August 4, 2008

Parts 2, 3 and 4 due: August 11, 2008

There is no Lab # 5 this quarter due to the fact that Summer Quarter is shorter.

Lab Sections and TA Office Hours
Harold Frank Hall, Room 1124 (DigiLab)

You may go to the office hours of any TA (not just the TA of your lab section)

Merritt Miller

merrittmiller@umail.ucsb.edu

Lab Section: Tuesday: 2:00 - 4:50 PM

Office hours: Monday: 3:20 - 4:40 PM

Sandeep Bhat

sandeepkbhat@umail.ucsb.edu

Lab Section: Tuesday 5:00 PM - 7:50 PM

Office hours: Monday: 4:40 - 6:00 PM

Wei Tang

w_tang@umail.ucsb.edu

Lab Section: Monday: 6:00 PM - 8:50 PM

Office hours: Monday: 2:00 - 3:20 PM

Acknowledgments: We would like to thank all the professors, TA's and lecturers, who have created, worked on, used, and revised the laboratories for this course. A partial list is as follows: Prof. Roger C. Wood, Christian Schmidt, Prof. Kaustav Banerjee, James Rosenthal, Brian Simolon, Dr. John M. Johnson, Prof. Volkan Rodoplu, Aida Todri, Nilesh Modi, Vishal Mehta, James Tandon. We would also like to thank Dr. John M. Johnson for preparing lecture note slides for this course, and for his continuing contributions during the summer quarters.

Practice Exams

ECE 152A Midterm Exam Fall 2004

ECE152A_Midterm Exam Winter 2005

ECE 152A Midterm Exam Fall 2005

ECE 152A Midterm Exam Fall 2007

ECE 152A Midterm Exam Winter 2008

ECE 152A Final Exam Fall 2004

ECE 152A Final Exam Winter 2005

Practice Problems for FSM Design: PS1 PS2 PS4

Lecture Notes (very rough)

(The following are handwritten lecture notes that I made while preparing for the lectures. These are very rough compared to the exposition in class, and were mostly notes to myself. However, I am providing them here in case you find them useful.)

. Lecture 5-6 Addendum

. Lecture 7

. Lecture 8-9

. FSM Examples

. Mealy/Moore Examples

. Blocking vs. Non-blocking Assignments