Events

PhD Defense: "Highly Scaled N-polar GaN MIS-HEMTs"

Dan Denninghoff

September 24th (Monday), 10:00am
Elings Hall 1601


The object of the research presented in this dissertation is developing a new type of transistor to be used in millimeter-wave monolithic integrated circuits (MMICs) for efficient power amplification in the W-band (75 – 110 GHz) and mm-band (110 – 300 GHz). Highly scaled N-polar GaN HEMTs (nitrogen-polar gallium nitride high electron mobility transistors) with novel low-parasitic T-gates were developed. It is well known that the large band gap and relatively high electron velocity of the GaN material system make GaN HEMTs excellent candidates for high-speed, high-power applications. However, it is less well known that N-polar GaN [000-1] has a number of materials and device advantages over the more mature and widely adopted Ga-polar GaN [0001] material system. These advantages include improved modulation efficiency and two-dimensional electron gas (2-DEG) confinement, lower sheet resistances in vertically scaled GaN channels, and lower contact resistances. These allow N-polar GaN HEMTs to be scaled with more immunity to short-channel effects than Ga-polar HEMTs.

Combining these N-polar GaN materials advantages with the advanced device design and technology developed in this dissertation, the HEMTs reported here demonstrate high gain, high frequency performance, high current, high breakdown voltage, low on-resistance, and relatively low dc-RF dispersion—all of which are required for efficient high-frequency power amplification. Devices made on both PAMBE (plasma-assisted molecular beam epitaxy) and MOCVD (metal-organic chemical vapor deposition) material with a newly designed (n+ GaN)/(UID GaN) ohmic re-growth scheme were investigated. Device performance highlights include 1650 mS/mm extrinsic transconductance (GaN record); 405 GHz maximum oscillation frequency, fmax (GaN record); 2.1 A/mm saturated drain current density (achieved at 0-V gate bias) with threshold voltage of -1.8 V; 190 V/µm device breakdown; and 0.25 Ω-mm on-resistance (GaN record).

A technique for accurately aligning these novel sub-100-nm T-gates in sub-200-nm source-drain regrowth regions was developed, which enabled the investigation of the effect of source-gate and source-drain spacing on device performance. Correlations between device dimensions and performance were examined, including a physics-based explanation of the tradeoffs in device design. This resulted in a clarified understanding of the device operating space, and showed how both high fT and high fmax may be obtained at the same bias point. Using a T-gate with an 85-nm gate length, an fT of 163 GHz and fmax of 405 GHz were obtained simultaneously. Moreover, the dimensions of the tall-stem T-gate structure were examined in order to simultaneously minimize gate parasitic capacitance and gate resistance, which are necessary for obtaining both high fT*Lg (cutoff frequency–gate length) values and high fmax values. The highest fT obtained using this process was 200 GHz with a 70-nm gate (14 GHz-µm) which is unprecedented for a gate of this length. This work shows how N-polar HEMTs with fT and fmax values above 500 GHz may be obtained.

Hosted by: Professor Umesh Mishra