Events

PhD Defense: "Compact Low-Power Low-Noise Neural Recording Wireless Channel for High Density Neural Implants (HDNIs)"

Mohamed Elzeftawi

October 18th (Thursday), 12:00pm
Harold Frank Hall, Rm 4164


Biomedical implants hold the promise to restore functionality for patients who have been afflicted by debilitating diseases. The most successful of these technologies has been the cochlear implant that has restored hearing to thousands of patients around the world. However, progress in the field of neural recording devices has been slower, largely due to the vast differences in scale when it comes to recording. Recording form hundreds or even thousands of electrodes in the motion cortex is necessary for precise movement control in 3-dimension. The design of low-power area-efficient circuits that allow for high-density neural recording is thus very crucial.

This thesis work presents the design, simulation and measured results of a compact low-power, low-noise frontend neural amplifier that utilizes current-feedback miller-compensation technique and occupies ∼ 0.0075mm2 of silicon area while consuming < 1.35μW of power from a 1.2V supply. The amplified analog signal is then digitized by a 2nd order ∆Σ analog-to-digital converter (ADC) that is based on a compact fully-differential self-biased amplifier. The core of the ADC consumes only 2.5μW from a 1.2V supply, when sampled at 1.6MHz, thus achieving a 60.5fJ/conversion-step FOM and occupies 0.012mm2 of chip area. This work also presents the design, simulation, and measured results of an impulse-radio ultra-wideband (IR-UWB) transmitter with measured datarates up to 105Mbps, average power consumption ≈ 1.4mW, and thus achieving a FOM ≈ 13pJ/bit. The transmitterʼs effective isotropic radiated power (EIRP) must fit within the mask defined by the Federal Communications Commission (FCC). Therefore, the oscillation frequency of the voltage-controlled oscillator (VCO), the pulse width, and the pulse amplitude are adjustable to ensure the transmitted pulseʼs power spectral density (PSD) fits within the FCC mask. The VCOʼs oscillation frequency is tuned through using an on-chip low-dropout (LDO) regulator that controls the VCOʼs supply voltage. Pulse-position modulation (PPM) was used as it is more noise immune and it breaks the periodicity in the transmitted pulses, thereby reducing the discrete tones that can otherwise show up in the PSD and potentially violate the FCC mask. Locking the oscillation frequency to the desired value is ensured through the use of a Phase Locked Loop with Embedded Digital Tracking. The PLLʼs reference frequency can be the frequency used for wireless power harvesting. The PLL acquires lock within ≈ 1μs, and afterward the VCO starts operating in pulsed PPM mode. Once the PLL locks, most of its blocks are disabled to save power. The PLL occupies an area ≈ 0.2mm2 including the IR-UWB transmitter and the LDO regulator. Chip fabrication was in 0.13μm CMOS technology.

About Mohamed Elzeftawi:

photo of mohamed elzeftawi Mohamed Elzeftawi received his B.S. degree with honors in Electronics and Communication Engineering in 2004 and his M.S. in Engineering Physics in 2007, both from Cairo University, Egypt. In 2008 he joined Prof. Luke Theogarajan's group in the Electrical and Computer Engineering Department at the University of California Santa Barbara to pursue his PhD degree. His PhD research interests are compact, low-noise, and low-power circuit design blocks for wirelessly powered high-density neural implants (HDNIs) to record brain activity. These circuit blocks include a neural amplifier, an IR-UWB transmitter, an LDO regulator, and a PLL.

Hosted by: Professor Luke Theogarajan