Events

PhD Defense: "Gate-Last InGaAs MOSFETs with Regrown Source-Drain Regions and ALD Dielectrics"

Andrew Carter

May 23rd (Thursday), 3:00pm
Engineering Science Building (ESB), Room 2001


III-V-based MOSFETs have the potential to exceed the performance of silicon-based MOSFETs due to the semiconductor’s small electron effective mass. Modern silicon-based MOSFETs with 22 nm gate lengths utilize high-k gate insulators and non-planar device geometries to optimize device performance. III-V HEMT technology has achieved similar gate lengths, but large source-drain access resistances and the lack of high-quality gate insulators prevent further device performance scaling. Sub-22 nm gate length III-V MOSFETs require metal-semiconductor contact resistivity to be less than 1 ohm-micron squared, gate insulators with less than 1 nm effective oxide thickness, and semiconductor-insulator interface trap densities less than 2E12 per square centimeter per electron volt.

This dissertation presents InGaAs-based III-V MOSFET process flows and device results to assess their use in VLSI circuits. Previous III-V MOSFET results focused on long (>100 nm) gate lengths and ion implantation for source-drain region formation. Scaling III-V MOSFETs to shorter gate lengths requires source-drain regions that have low sheet resistance, high mobile charge densities, and low metal-semiconductor contact resistance. MBE- and MOCVD-based raised epitaxial source-drain regrowth meet these requirements. MBE InAs source-drain regrowth samples have shown 0.5 to 2 ohm-micron squared metal semiconductor contact resistivities. MOCVD InGaAs source-drain regrowth samples have shown < 100 ohm-micron single-sided access resistance to InGaAs MOSFETs. Gate insulators on III-V materials require large conduction band offsets to the channel, high dielectric permittivities, and low semiconductor-insulator interface trap densities. An in-situ hydrogen plasma / trimethylaluminum treatment has been developed to lower the gate semiconductor-insulator interface trap density. This treatment, done immediately before gate insulator deposition, has been shown to lower MOS capacitor interface trap densities by more than a factor of two. Devices using gate-first MBE regrowth, gate-last MBE regrowth, and gate-last MOCVD regrowth were fabricated and resulting devices characterized. 65 nm gate length gate-first MBE regrowth devices employing a 2.2 nm EOT Al2O3 gate insulator show peak transconductances of 0.3 mS/micron at 1 V Vds. Gate-first FET performance scaling is limited by processed-induced damage and ungated access regions. 64 nm gate length gate-last MBE regrowth devices employing a 1.21 nm EOT Al2O3 / HfO2 bi-layer gate insulator show peak transconductances of 1.4 mS/micron at 0.5 V Vds. Other gate-last MBE samples had long channel subthreshold swings as low as 117 mV/dec. 48 nm gate length gate-last MOCVD MOSFETs employing a 0.8 nm EOT HfO2 gate insulator and digital channel etching show peak transconductances of 2 mS/micron at 0.5 V Vds, with long channel devices having 97 mV/dec subthreshold swing.

About Andrew Carter:

photo of andrew carter Andrew Carter graduated with a Bachelor of Science in Electrical Engineering from the University of Notre Dame in 2008. At Notre Dame, he worked under Prof. Gary H. Bernstein on electron beam lithography, high-resolution scanning electron microscopy, and heterogeneous substrate interconnects. He is currently pursuing a Ph.D. in Electrical and Computer Engineering with an emphasis on Electronics and Photonics. His research interests include III-V MOSFET device physics, fabrication, and characterization.

Refreshments will be provided

Hosted by: Professor Mark Rodwell