Vivek S NandakumarJanuary 10th (Friday), 10:00am
Microprocessor architectures are evolving at a pace greater than ever before, primarily driven by the rapidly growing mobile industry. To meet the industry’s stringent power, performance and cost demands there is a rising trend towards building heterogeneous processors with both CPU cores and off-chip components on the same chip. Multicore heterogeneous processors significantly improve energy efficiency due to reduced off-chip communication and allow for customization of the heterogeneity composition which can be varied to fit a wide range of platforms and workload conditions. A comprehensive system-level analysis to explore architectural solutions thus becomes critical to find properly matched architectures with optimal power and performance characteristics. We observe that heterogeneous systems’ behavior becomes increasingly sensitive to changes in the low-level physical attributes – the processor’s floorplan, layout, or device technology. We also observe that accounting for physical design parameters can lead to considerably different architectural choices when the application characteristics executed on heterogeneous architectures change. Very few system level analysis frameworks to analyze heterogeneous architectures exist and they do not account for physical design effects. Physical design parameters are usually available at a much later stage in the design process when the parameters are optimized independently of system-level parameters as it is too late to modify the architecture at this point.
In this thesis, we develop a physically aware exploration framework and provide several synthetic heterogeneous applications that allow for a comprehensive evaluation of various architectural and physical design configurations under different workload conditions. We introduce several architectures that achieve significant all around improvement in system characteristics that could be attributed to the fact that physical design parameters are considered at the system-level. We show that ignoring physical design aspects leads to sub-optimal architectures for particular application categories.
We show that an unexplored potential for performance improvement and significant energy savings exists when pure physical design based alternatives such as 3D stacking and emerging devices like Vertical Slit Field Effect Transistors (VeSFETs) can be traded-off along with architectural options and software application characteristics at the system level. Physically aware system-level models provide vital insights needed to develop and test novel architectural solutions that uniquely exploit features of emerging technologies. We discuss the distinct features and advantages of such architectures which are possible only due to the knowledge of the underlying physical attributes.
About Vivek S Nandakumar:
Vivek S Nandakumar is a PhD candidate in the Electrical and Computer Engineering Department, Univ. of California, Santa Barbara, guided by Professor Malgorzata Marek-Sadowska. He holds a Master's degree in Electrical and Computer Engineering from the University of Arizona and Bachelor's degree in Electronics and Communication from the University of Madras, India. He has interned at Intel in Hillsboro, AMD in Austin, and AMD Research in Santa Clara during the course of his studies. His research interests include heterogeneous architectures (CPU+GPU), 3D stacking using novel devices, and on-chip interconnection networks (NoCs).
Hosted by: Professor Malgorzata Marek-Sadowska