Events

PhD Defense: "Hierarchical Transactions for Hardware/Software Cosynthesis"

Kunal Arya

September 12th (Friday), 3:00pm
Harold Frank Hall, Room 1132 (CS Conf. Rm.)


The race to fulfill Moore’s Law has lead to billion-scale transistor density, enabling ubiquitous and computationally diverse architectures. These device technologies have shaped the system-on-a-chip (SoC) landscape, opening new design opportunities in field-programmable gate arrays (FPGAs), hybrid FGPAs, full custom integrated chips, and commercial fixed-architecture platforms. The common thread across these platforms is the integration of distributed memories (including cached hierarchies), computational pipelines, and communication ports/networks. Making efficient use of these components, however, is an enormous challenge. Automated cosynthesis addresses the challenge through optimized partitioning, scheduling, mapping, and binding of an application onto heterogeneous systems.

This research introduces the hierarchical transaction model, a formal, abstract model of computation designed to enable synthesis across the varying semantic and execution models pervasive in heterogeneous systems. This novel specification-to-silicon methodology copes with changing architectures, enabling structured cosynthesis that is resilient to shifting constraints. High-level application behavior is codified through a carefully constructed semantic model ensuring robust design methodology, verifiable concurrent models, and maximal exploitation of parallelism. It further leverages a unique data/execution hierarchical encapsulation framework to guarantee scalable analysis.

At the front end, the model is represented with a practical, understandable specification language that encourages concise design of complex applications. The language focuses designer intent through specific limitations in how state is accessed. The benefit of transactional interactions empowers designers with tools to directly identify and address concurrency bugs. The language is structured with synthesis in mind — it provides methods of expression that are confined to actions commensurate with optimization. Designers express families of valid executions in a minimal format through high-level dependencies, type systems, and computational relationships.

This defense introduces the Hierarchical Transactional Language, its underlying semantic model, along with its compiler, simulator, and studies into high performance synthesis. Everyone is welcome!

About Kunal Arya:

Kunal Arya received a B.S. with Honors in Computer Engineering from the University of Calfornia, Santa Cruz in 2007. He earned a Master's in Electrical and Computer Engineering at University of California, Santa Barbara. His research under Professor Forrest Brewer has focused on automated design methodologies and specification systems, particularly for complex reconfigurable platforms. His interests span compiler design, automated synthesis heuristic design, reconfigurable architectures, and verification systems.

Hosted by: Professor Forrest Brewer