Events

PhD Defense: "Realization and Formal Analysis of Asynchronous Pulse Communication Circuits"

Merritt Miller

December 12th (Friday), 11:45am
Elings Hall, Room 1605


This work presents an approach to constructing asynchronous pulsed communication circuits. These circuits use small delay elements to introduce a gate-level sense of time, removing the need for either a clock, or a handshaking signal to be part of a high-speed communication link. This construction method allows the creation of links with better than normal jitter tolerance, allowing for simple circuit architectures that can easily be made robust to soft error.

A 5Gbps radiation-hardened link, targeted at use in detector modules at the LHC, will be presented. This application presents a special challenge due to both very high radiation levels (1MGy+ lifetime dose) and the demand for minimum material use. The presented link, realized in 130nm technology, is unique in that it is lower power (~50mW end to end) and lower area 0.12mm^2 including ESD protection and I/O amplifiers. Due to its asynchronous construction and the gate design style, the link essentially has no power dissipation when idle, and enters and exits its idle state with no delay.

In addition to the construction of the link, this presentation covers the design and analysis methodology that can be used to create communication components attached to the link. The methodology used to construct the serializer, deserializer, and self-test circuitry for the link has the capacity to create fast logic circuits. In this case, a 5Gbps SER/DES and a 2GHz RNG are implemented in 130nm CMOS technology using a gate design style that does not dissipate static power.

About Merritt Miller:

Merritt Miller received his Bachelors in Electrical Engineering from UCSB in 2007 and his Masters in Electrical and Computer Engineering from UCSB in 2009. He is currently a researcher in Forrest Brewer's research group focusing on radiation hardened high-speed serial links. His is also involved in research on formal analysis of AMS circuits, continuous-time system description, fault tolerant network topology, and development of control system hardware.

Hosted by: Professor Forrest Brewer