Events

"CNSE- SUNY Polytechnic Institute: A Nanoelectronics Overview"

Michael Liehr, Executive Vice President of Innovation and Technology, CNSE- SUNY Poly

January 26th (Monday), 3:00pm
Engineering Science Building (ESB), Rm 2001


One approach to the role of universities in economic development involves a close collaboration between universities and State government, enabling the settlement of established companies at or close to campuses, typically via science or industrial parks. Here, physical proximity of commercial enterprises allows the use of university infrastructures as well as the training and recruitment of specialized skills needed by the companies. At CNSE, this approach has been used extensively with an initial focus on nano-electronics and will be described using specific consortia examples.

The capabilities of the CNSE campus will be detailed using the challenges to the traditional scaling model as the theme. The nanoelectronics industry has enjoyed decades of productivity gains driven by lithographic scaling. However, scaling slowed due to delays in the introduction of extreme ultraviolet (EUV). New materials were introduced which help to drive increases in performance or reductions in power consumption. However, to maintain the pace of die-level cost reduction, two other approaches are being pursued, a transition in wafer size to 450mm and chip stacking. All three face the challenge of becoming cost-effective prior to wide-spread adoption. Lastly, the equipment industry is challenged to develop novel materials solutions as required for device scaling in parallel for 300mm and 450mm.

The first generation of EUV production scanners will be used for development of sub-10nm technology node CMOS, as well as to support advanced resist and mask development. Chip stacking technologies, either via interposers (“2.5D”) or chip stacks (“3D”), are being developed, yet no standard integration scheme has emerged yet due to constraints in yield management or limitations in equipment cost of ownership. The timely availability of novel materials in conjunction with a manufacturable process is critical for continued scaling. The recent re-assessment by G450C of the likely CMOS node for the wafer transition opens up a new set of process options to evaluate, based on the industry introduction of materials needed for sub-10nm CMOS.

About Michael Liehr:

photo of Michael LiehrAs SUNY Polytechnic Institute Executive Vice President of Innovation and Technology, Michael Liehr focuses on the creation of new business opportunities and manages integrated industry-university consortia and public-private partnerships. He is also responsible for the effective and efficient operation of the CNSE core strategic CMOS semiconductor and packaging partnership engagements, including the IBM, GLOBALFOUNDRIES, SEMATECH, AMAT, TEL, and LAM partnerships. Dr. Liehr is further the Vice President for Research at Polytechnic Institute. In this role, he leads the State University of New York’s Network of Excellence in Materials and Manufacturing. Prior to this assignment, he led the Global 450mm Consortium through the start-up phase as the General Manager. Prior to joining SUNY Polytechnic Institute and the College of Nanoscale Science and Engineering (CNSE), Dr. Liehr served as an IBM executive responsible for Worldwide Semiconductor Manufacturing Strategic Production Alliances for leading-edge semiconductor products. While at IBM T.J. Watson Research, he led the Research Divisions Microelectronics Manufacturing Research program.

Hosted by: Professor John Bowers