Events

PhD Defense: "III-V Ultra-Thin-Body InGaAs/InAs MOSFETs for Low Standby Power Logic Applications"

Cheng-Ying Huang

August 14th (Friday), 3:00pm
Engineering Science Building (ESB), Rm 1001


As the device scaling beyond sub-10-nm regime, III-V InGaAs/InAs MOSFETs are promising candidates for replacing Si-based MOSFETs for future VLSI logic applications. III-V InGaAs materials have low electron effective mass and high electron velocity, allowing higher on-state current at lower Vdd and reducing the switching power consumption. However, III-V InGaAs materials have a narrower band gap and higher permittivity, leading to large band-to-band tunneling (BTBT) leakage at the drain end of the channel, and large subthreshold leakage due to worse electrostatic integrity. To utilize III-V MOSFETs in future logic circuits, III-V MOSFETs must have high on-state performance over Si MOSFETs as well as very low leakage current with low standby power consumption. In this talk, we will report three techniques for the reduction of leakage currents in InGaAs/InAs MOSFETs, as described below.

1) Wide band-gap barriers: We developed AlAs0.44Sb0.56 barriers lattice-matched to InP using molecular beam epitaxy, and studied the electron transport in In0.53Ga0.47As/AlAs0.44Sb0.56 heterostructures. We also demonstrated the reduction of barrier leakage on InGaAs MOSFETs using AlAs0.44Sb0.56 back barriers and p-doped In0.52Al0.48As barriers.

2) Ultra-thin channels: We investigated the electron transport in InGaAs and InAs ultra-thin quantum wells and ultra-thin body MOSFETs (tch~2-4 nm). For high performance logic, InAs channels enable higher on-state current, while for low power logic, InGaAs channels allow lower BTBT leakage current.

3) Source/Drain engineering: We developed raised InGaAs and recessed InP source/drain spacers. The source/drain spacers improve electrostatics, reducing subthreshold leakage, and smooth the electric field near drain, reducing BTBT leakage. With the further replacement of raised InGaAs spacers by the recessed, doping-graded InP spacers at high field regions, BTBT leakage can be reduced ~100:1.

Using the above-mentioned techniques, record high performance InAs MOSFETs were demonstrated with Ion = 500 μA/μm at Ioff = 100 nA/μm and Vds=0.5 V, showing comparable on-state performance to 22 nm Si FinFETs. Record low leakage InGaAs MOSFETs were also demonstrated with minimum Ioff = 60 pA/μm at 30 nm-Lg. This recessed InP source/drain spacer technique enables III-V MOSFETs for low standby power logic applications. Furthermore, InAs MOSFETs fabricated on Si substrates exhibit high yield, and high peak transconductance gm~2.0 mS/μm at 20 nm-Lg and Vds=0.5 V. With further scaling of gate length, a 12 nm-Lg III-V MOSFET has shown maximum Ion/Ioff>8.3·10^5, confirming that III-V MOSFETs can scale to sub-10-nm technology nodes.

About Cheng-Ying Huang:

Cheng-Ying Huang received his B.S. degree in Materials Science and Engineering and minor degree in Electrophysics in 2007 from National Chiao Tung University, Taiwan. He received M.S. degree in Graduate Institute of Electronics Engineering in 2009 from National Taiwan University, Taiwan. He joined Taiwan Semiconductor Manufacturing Company in 2010, working on Si/SiGe source/drain regrowth on Si FinFETs. He is currently a PhD candidate in Electrical and Computer Engineering, UC Santa Barbara. He is currently involved in III-V MOSFET research efforts under supervision of Professor Mark Rodwell and Professor Arthur Gossard.

Hosted by: Professor Mark Rodwell