"Another Inconvenient Truth: Snails Are More Intelligent Than Us"

Dr. T. W. Williams, Consultant & Synopsys Fellow – Retired

February 1st (Monday), 10:45am
Engineering Science Building (ESB), Rm 1001

For decades there has been a new CMOS technology node approximately every two years. Until recently, thanks to scaling, the key feature of every new technology node has been a 100% integration capacity and 40% performance improvement… free-of-charge. The International Technology Roadmap for Semiconductors (ITRS) has been architected in such a way that this improvement became a self-fulfilling prophecy of the roadmap itself. Everything else has been bent in the attempt to make scaling happen… forever.

For eons snails have built the cells of their shell according to the Fibonacci’s numbers: 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233, 377, 610, 987, etc. – where each cell has a volume that is the sum of the volume of the previous two cells. Snails understand, however, that at a certain point in time growth must stop to prevent the collapse of the shell by making it too big and therefore fragile. When this point is reached, snails do stop adding larger cells, and start improving the robustness of the shell.

Back to us: technology-wise, scaling has rapidly exhausted the resources of CMOS technology, which, by now, struggles to deliver any further improvement. Economy-wise, Dr. Gordon Moore once observed:

“what we end up doing is really selling real estate. We’ve sold area on the silicon wafer for about a billion dollars an acre, that order of magnitude, as long as I’ve been in the industry“[1]

In order to stay afloat, the semiconductor industry would need to double the number of units it sells, from one technology node to the next. Not only is this clearly impossible, but it puts the semiconductor suppliers on a collision course with their customers, who are now looking for half the silicon area from one technology node to the next. Atoms don’t scale, and markets are finite.

As decimated vanguards approach the 32-nanometer node and start planning the jump to the 22-nanometer node, a number of fundamental challenges are emerging, both technical and financial, which force a thorough rethinking of how scaling has been done, and whether scaling continues to be the most appropriate solution to provide the world with the silicon content that it needs.

Like Al Gore’s premise on energy consumption and global warming, there is an inconvenient truth to be acknowledged in our industry: scaling is like fossil fuels – the cheapest and easiest way to go. Unfortunately, also like fossil fuels, it is not sustainable indefinitely. And it becomes more costly and inefficient every day. New avenues, which are available today, are worth exploring and must be undertaken. That is, unless snails are more intelligent than us…

In this keynote, Dr. Williams will describe the problems with scaling and a number of possible solutions, including the latest alternative paths and their relative merits.

About Dr. T. W. Williams:

photo of t.w. williams Dr. Thomas W. Williams is a Consultant in the area of Electronic Design Automation. Prior to that he was a Synopsys Fellow at Synopsys in Boulder, Colorado, U.S.A. Formerly, he was with IBM Microelectronics Division and manager of the VLSI Design for Testability group. He received a B.S.E.E. from Clarkson University, an M.A. in pure mathematics from the State University of New York at Binghamton, and a Ph.D. in electrical engineering from Colorado State University. He has received numerous best paper awards from the IEEE and ACM, is the founder or co-founder of a number of workshops and conferences dealing with testing, and was twice a Distinguished Visitor lecturer for the IEEE Computer Society. Dr. Williams has previously served on the Computer Society Board of Governors and the IEEE Board of Directors, and was the Society's 2000 Treasurer. He is a member of the Eta Kappa Nu, Tau Beta Pi, IEEE, ACM, Sigma Xi, and Phi Kappa Phi. He is an Adjunct Professor at the University of Calgary, Calgary, Alberta, Canada; and in 1985 and 1997, he was a Guest Professor and Robert Bosch Fellow at the Universitaet of Hannover, Hannover, Germany. He was recently honored as a foreign member of the Chinese Academy of Science. Dr. Williams was named an IEEE Fellow in 1988 and received the Computer Society's W. Wallace McDowell Award for outstanding contributions to the computer art in 1989. In 2007 Dr. Williams received the European Design and Automation Association Lifetime Achievement Award for "outstanding contributions to the state of the art in electronic design, automation, and testing of electronic systems." In 2010 Dr. Williams received the Distinguished Alumni Award Colorado State University, College of Engineering. That same year he also received the IEEE TTTC Lifetime Contribution Medal.

Hosted by: Professor Li-C. Wang