Events

PhD Defense: "Towards Data Reliable, Low-Power, and Repairable Resistive Random Access Memories"

Amirali Ghofrani

March 8th (Tuesday), 12:30pm
Engineering Science Building (ESB), Rm 2001


A series of breakthroughs in memristive devices have demonstrated the potential of memristor arrays to serve as next generation resistive random access memories (ReRAM), which are fast, low-power, ultra-dense, and non-volatile. However, memristors’ unique device characteristics also make them prone to several sources of error. Owing to the stochastic filamentary nature of memristive devices, various recoverable errors can affect the data reliability of a ReRAM. Permanent device failures further limit the lifetime of a ReRAM. This dissertation is an effort toward more reliable and longer-enduring ReRAM systems by employing low-power solutions.

We look into a data reliability issue known as write disturbance. Writing into a memristor in a crossbar could disturb the stored values in other memristors that are on the same memory line as the target cell. Such disturbance is accumulative over time which may lead to complete data corruption. As a solution, we propose the use of two regular memristors on each word-line as “canary cells”. The canary cells keep track of the disturbance accumulation and trigger a refresh to restore the weakened data, when necessary.

We also investigate the considerable variation in the write-time characteristics of individual memristors. With such variation, conventional fixed-pulse write schemes not only waste significant energy, but also cannot guarantee reliable completion of the write operations. We address such variation by proposing an adaptive write scheme that adjusts the width of the write pulses for each memristor. Our scheme embeds an online monitor to detect the completion of a write operation and takes into account the parasitic effect of line-shared devices in access-transistor-free memristive arrays. We further investigate the use of this method to shorten the test time of memory march algorithms by eliminating the need of a verifying read right after a write, which is commonly employed in the test sequences of march algorithms.

Finally, we propose a novel mechanism to extend the lifetime of a ReRAM by protecting it against hard errors through the exploitation of a unique feature of bipolar memristive devices. Our solution proposes an unorthodox use of complementary resistive switches (a particular implementation of memristive devices) to provide an “in-place spare” for each memory cell at negligible extra cost. The in-place spares are then utilized by a repair scheme to repair memristive devices that have failed at a stuck-at-ON state at a page-level granularity. Further, we explore the use of in-place spares in lieu of other memory reliability and yield enhancement solutions, such as error correction codes (ECC) and spare rows. We demonstrate that with the in-place spares, we can yield the same lifetime as a baseline ReRAM with either significantly fewer spare rows or a lighter-weight ECC, both of which can save on energy consumption and area.

About Amirali Ghofrani:

photo of amirali ghofraniAmirali received his B.Sc. in computer engineering from the University of Tehran, Iran, in 2007, and two M.Sc. degrees in computer engineering from the University of Tehran, Iran, and University of California Santa Barbara in 2010 and 2013. His main research focus is on addressing variation and reliability issues of memristive memories and finding novel applications for them. His other research interests include reliability and testing of Network on Chip interconnections, high level synthesis of Transaction Level Models (TLM), and assertion based verification. He has more than 20 publications in these research areas. He was the recipient of the 2011 International Test conference Best Paper award, 2013 IEEE Philadelphia Section & Test Technology Technical Council Gerald W. Gordon service award, and several leadership awards in UCSB.

Hosted by: Professor Kwang-Ting Cheng, SoC Design and Test Lab