Events

PhD Defense: "Test Data Analytics: Exploration of Hidden Patterns for Test Cost Reduction and Silicon Characterization"

Chun-Kai Hsu

March 23rd (Wednesday), 11:30am
Harold Frank Hall (HFH), Rm 4164 (ECE Conf. Rm.)


The manufacturing process for a modern integrated circuit encounters excessively long test time and produces huge amount of test data. There is valuable information hidden in the test data about the device under test (DUT), far more than the binary go/no go classification. Exploring the hidden correlations and patterns in the test data allows better understanding of the DUT and therefore leads to broad applications, such as test cost reduction and silicon characterization for discovering parametric variations and weak links in manufacturing process. A methodology with supporting statistical learning algorithms for test time and cost reduction through exploiting both spatial and inter-test-item correlations in the test data is proposed. A case study of a high-volume industrial device demonstrates that some test items can be identified for removal from the test program without compromising test quality and shows the significant reduction of test time. Next, a framework for characterizing systematic variations and failures through exploring the hidden patterns of test data from multiple test stages is developed. Experimental results demonstrate that the proposed framework reveals comprehensible and significant correlations in an industrial test dataset. Moreover, a software toolbox dedicated to test data analytics is also developed. The toolbox provides flexible and scalable functions for parsing, processing, learning and display test data for both designers and users in the area of test data analytics.

About Chun-Kai Hsu:

photo of Chun-Kai HsuChun-Kai Hsu received his B.S. and M.S. degree from the Electrical Engineering department in National Tsing Hua University, Taiwan, in 2006 and 2008, respectively. He is a PhD Candidate in the Electrical and Computer Engineering Department at the University of California, Santa Barbara. His main research focus is on data mining and statistical learning techniques that target VLSI production test data for test cost reduction and silicon characterization. He has interned with Texas Instruments and GLOBALFOUNDRIES, developing algorithms for test time reduction and systematic failures characterization. His other interests include embedded system and Linux kernel/system.

Hosted by: Professor Tim Cheng