Events

PhD Defense: "Heterogeneous Integrated Photonic Transceiver on Si"

Chong Zhang

June 30th (Thursday), 11:00am
Elings Hall, Room 1605


The demand for high-speed and low-power consumption short-distance data links, especially for inter-chip communications for future super com, has led to great efforts to develop high density photonics integrated circuits with low cost and large bandwidth. Silicon photonic integrated circuits (PICs) 3D integrated with electronic integrated circuits promise future high-speed and cost-effective optical interconnects to enable Exascale performance computers and datacenters. For realistic intra-chip and inter-chip optical links, the bandwidth density and total power consumption are major challenges. Consequently, full integration of all photonics components on chip, including high speed modulators and photodetectors, and especially lasers, is needed for scalable and energy efficient system topology designs.

A library of functional devices has been developed on silicon with the heterogeneous integration method, including ultralow loss waveguides, arrayed waveguide grating (AWG) routers, low threshold distributed feedback (DFB) lasers, high speed electroabsorption modulators (EAM), semiconductor optical amplifiers (SOA) and photodetectors (PD) on silicon, enabling a large scale photonic integration implementation. In this work we demonstrate a high speed heterogeneous integrated circuit on silicon for chip level interconnection and network. Wavelength-division multiplexing (WDM) transceiver network was integrated on a single chip with over 400 active and passive components. With the heterogeneous integration approach, each type of device was optimized individually and show high performance in the integrated circuit. The reconfigurable photonic NoC circuit with large bandwidth transceivers promises a solution for future low cost and large bandwidth chip level interconnections.

Hosted by: Professor John E. Bowers