Xinjie GuoMarch 14th (Tuesday), 4:30pm
Nervous systems inspired neurocomputing has shown its great advantage in object detection, speech recognition and a lot of other machine-learning technology-driven applications from speed and power efficiency. Among handful neurocomputing implementation approaches, analog nanoelectronic circuits are very appealing because they may far overcome digital circuits of the same functionality in circuit density, speed and energy efficiency. Device density is one of the most essential metrics for designing large-scale neural networks, allowing for high connectivity between neurons. Thanks to the high-density nature of traditional memory applications, building artificial neural networks with hybrid complementary metal oxide semiconductor (CMOS)/memory devices would enable the high parallelism as well as achieve the performance advantages.
In this talk, we focus on efficiently implementing synapses, the most numerous elements of neural networks, by memory devices. This application, however, imposes a number of requirements, such as the continuous change of the memory resistance state, creating the need for novel engineering approaches. Here we report such engineering approaches for advanced commercial 180-nm ESF1 and 55-nm ESF3 NOR flash memory, facilitating fabrication and successful test of high performance analog vector-by-matrix multiplication which is the key operation performed at signal propagation through any neuromorphic network. Furthermore, we present the recent progress toward neuromorphic computing implementations based on nonvolatile floating-gate devices, in particular the experimental results for a prototype 28×28-binary-input, 10-output, 3-layer neuromorphic network based on arrays of highly optimized embedded nonvolatile floating-gate cells. The fabricated neuromorphic network’s active components, including 101,780 floating-gate cells, have a total area below 1 mm2. The network has shown a 94.7% classification fidelity on the common MNIST benchmark, close to the 96.2% obtained in simulation. The classification of one pattern takes sub-1 μs time and sub-20 nJ energy – both numbers much better than for the best reported digital implementations of the same task.
About Xinjie Guo:
Xinjie Guo received her Bachelor’s degree in Microelectronics from Peking University, China in 2011 and her Master’s degree in computer engineering from UCSB at 2013. Now she is pursuing a Ph.D. degree in Computer Engineering at UCSB under the supervision of Prof. Dmitri Strukov. Her research focuses on applying non-volatile memory technologies for power efficient and high performance neural networks. .
Hosted by: Professor Dmitri Strukov