Rui WuMarch 27th (Monday), 4:30pm
Optical interconnects have started to replace electrical interconnects in the communications between racks and circuit boards with potential benefits in bandwidth, delay, power efficiency, and crosstalk. Silicon photonics has emerged to be a highly promising enabling technology for the short-reach nanophotonic interconnects because it offers favorable CMOS compatibility and high integration level. The fast-growing complexity of photonic integrated circuit (PIC) and close electro-optical integration call for computer-aided design (CAD) for integrated photonics, and electro-optical design automation (EPDA) including accurate behavior models and efficient simulation methodologies for integrated electro-optical systems. Also, the nanophotonic devices are highly sensitive to fabrication process variation and thermal variation effects. To address these challenges, I will present two parts of efforts in my talk: (1) compact modeling and circuit-level simulation of nanophotonic interconnects, and (2) power-efficient management of the variation effects in nanophotonic interconnects.
We develop compact models for key components in nanophotonic interconnects including silicon microring modulators and other key components. These compact models are developed based on their electrical and optical properties and are then extensively validated by measurement data. The model parameters are extracted from common electrical and optical tests. Implemented in Verilog-A, the models are used in SPICE simulations of optical links. The compact model library and the simulation methodology enable electro-optical co-simulations and optical device design explorations in the circuit-level.
To address the variation challenges, we propose several modeling methods and power-efficient management schemes. The proposed adaptive tuning technique performs on-chip self-tests and adaptively allocates just enough power for link operations. The technique saves significant amount of power compared to worst-case based conservative designs, and scales well w.r.t. variations and network size. We also design power-efficient pairing algorithms for microring-based optical interconnects. Our algorithms optimally mix-and-match microring-based devices to minimize the power consumption for tuning. The algorithms are tested on both measured and synthetic data sets, demonstrating promising results of power reduction and scalability for handling a large number of devices. Lastly, we decompose and analyze wafer-scale spatial patterns of process variations in microring modulators, providing useful insights in understanding the process variation sources.
About Rui Wu:
Rui Wu received his B.S. in Automation from Tsinghua University, Beijing, China in 2012, after which he joined the SoC Design and Test Lab at ECE Department, UCSB. His research interests are in modeling and design of nanophotonic interconnect systems, silicon photonics, computer-aided design (CAD) and testing of VLSI. He interned in the Large-Scale Integrated Photonics (LSIP) group at Hewlett-Packard Labs during the summers of 2014, 2015, and 2016.
Hosted by: Professor Tim Cheng