Events

PhD Defense: "Modeling, Fabrication, and Analysis ofVertical Conduction Gallium Nitride Fin MOSFET"

Maher Tahhan

August 18th (Friday), 2:00pm
Elings Hall, Room 1605


Gallium Nitride has seen much interest in the field of electronics due to its large bandgap and high mobility. In the field of power electronics, this combination leads to a low on-resistance for a given breakdown voltage. To take full advantage of this, vertical conduction transistors in GaN can give high breakdown voltages independent of chip area, leading to transistors with nominally low on resistance with high breakdown at a low cost.

Acknowledging this, a vertical transistor design is presented with a small footprint area. This design utilizes a fin structure as a double gated insulated MESFET with electrons flowing from the top of the fin downward. The transistor’s characteristics and design is initially explored via simulation and modelling. In this modelling, it is found that the narrow dimension of the fin must be sub-micron to allow for the device to be turned off with no leakage current and have a positive threshold voltage.

Several process modules are developed and integrated to fabricate the device. A smooth vertical etch leaving low damage to the surfaces is demonstrated and characterized, preventing micromasking during the GaN dry etch. Methods of removing damage from the dry etch are tested, including regrowth and wet etching. Several hard masks were developed to be used in conjunction with this GaN etch for various requirements of the process, such as material constraints and self-aligning a metal contact. Multiple techniques are tested to deposit and pattern the gate oxide and metal to ensure good contact with the channel without causing unwanted shorts.

To achieve small fin dimensions, a self-aligned transistor process flow is presented allowing for smaller critical dimensions at increased fabrication tolerances by avoiding the use of lithographic steps that require alignments to very high accuracy. In the case of the device design presented, the fins are lithographically defined at the limit of i-line stepper system. From this single lithography, the sources are formed, fins are etched, and the gate insulator and metal are deposited.

The first functional fabricated devices are presented, but exhibit a few differences from the model. A threshold voltage of -6 V, was measured, with an ID of 5 kA/cm2 at 3 V, and Ron of 0.6 mΩ/cm2. The current is limited by the Schottky nature of the top contacts and show a turn-on voltage as a result. These measurements are comparable to recently published GaN fin MOSFET data, whose devices were defined by e-beam lithography. This dissertation work sought to show that a vertical conduction fin MOSFET can be fabricated on GaN. Furthermore, it aimed to provide a self-aligned process that does not require e-beam lithography. With further development, such devices can be designed to hold large voltages while maintaining a small footprint.

About Maher Tahhan:

m. tahhan Maher Tahhan is a UCSB PhD student in the Mishra Group working on vertical GaN transistors.




Hosted by: Professor Umesh Mishra