Events

PhD Defense: "Rescuing Moore’s Law with Two-Dimensional Van der Waals Materials"

Wei Cao

October 18th (Wednesday), 3:30pm
Elings Hall, Rm 1601


Moore’s law, which has been guiding the development of integrated circuits (IC) industry over six decades, is facing unprecedented challenges, because of severe short-channel effects and unaffordable fabrication cost of silicon based sub-10 nm metal-oxide-semiconductor field-effect transistors (MOSFETs). The emerging two-dimensional (2D) Van der Waals materials provide an ideal platform for ultra-short channel FETs due to their unique properties, and hence can potentially extend Moore’s law into forthcoming sub-10 nm technology nodes. My doctoral research is focused on exploring, both theoretically and experimentally, the performance and scalability of 2D materials based logic/memory devices for next-generation very-large-scale-integration (VLSI) circuits.

The theoretical work can be divided into two parts. The first is analytical modeling of 2D FETs and tunnel FETs, which provides straightforward physical insight/guidance into the device design and optimization, and paves the way for large-scale 2D circuit exploration. The second is developing a non-equilibrium Green function (NEGF) based quantum transport simulator (over 3000 lines of Matlab code) to evaluate/predict the intrinsic or upper-limit performance and scalability of 2D logic (FETs and tunnel FETs) and memory (floating gate transistors) devices. It is found that the ultrathin body and unique properties of 2D materials allow FETs, tunnel FETs and floating gate transistors made of them scalable up to 5-6 nm channel length, without compromising device performance. By judiciously selecting 2D materials for the channel and floating gate, a novel retention mechanism is found achievable and can improve the lifetime of NAND FLASH by more than one order. Moreover, by taking key parameters for transport, such as effective mass, and mobility etc., as variables for extensive multi-dimensional simulations, a performance phase diagram is constructed. Through this diagram, it is found that among various 2D semiconductors, black phosphorus (BP) and WSe2 are the most promising candidates for high-performance (HP) and low-standby-power (LSTP) applications, respectively, at 6 nm channel length scale. This work unambiguously charts the research direction and paves the pathway for experimentalists in the 2D electronics arena.

The experimental contribution also has two parts. The first is demonstrating a 10-nm-scale top gated single layer MoS2 FET without resorting to the high-cost and/or low-throughput electron beam lithography, for the first time. The gate/channel of this device is defined with 6-nm Al2O3 wrapped metallic Si2Co nanowire, which is obtained through chemical synthesis. The scalability of this device is evaluated with quantum transport simulation, and proved to be scalable to 6 nm. The second contribution is realizing a novel polarity programmable CMOS device that is entirely made of 2D materials, specifically tungsten diselenide (WSe2), graphene, and hexagonal boron nitride (h-BN). The polarity programmability is achieved by adding an extra control (or programming) gate on one of the two contacts of a Schottky barrier FET, to modulate the Schottky barrier contact to n-type or p-type. Demonstrated device shows clear unipolarity and high current level. Device performance can be further improved by suppressing defect density in WSe2, and by using 2D high-k gate dielectric. This polarity programmable 2D device renders exponential functionality increase to circuits/chips, i.e., the cost per functionality is significantly reduced, thereby opening up a revolutionarily new pathway to sustain Moore’s law forever.

About Wei Cao:

photo of wei cao Wei Cao is a Ph.D. Candidate and Graduate Student Researcher in the Nanoelectronics Research Laboratory (NRL), Department of Electrical and Computer Engineering at University of California, Santa Barbara, CA, advised by Prof. Kaustav Banerjee. His doctoral research has played a pioneering role in the exploration of 2D logic/memory device, leading to a number of breakthrough device innovations in NRL, uniquely enabled by 2D materials. He has published 14 first-author, and 20 coauthored peer-reviewed papers in high-impact journals (including Nature, Nano Lett., ACS Nano, Adv. Mater., IEEE EDL, and IEEE TED etc.) and top conferences (such as IEEE IEDM), which have received nearly 500 citations (as of Oct. 2017) with an h-index of 12.

Hosted by: Professor Kaustav Banerjee