Bluespec System Verilog (BSV) is aimed at hardware designers who are using or expect to use Verilog, VHDL, or System Verilog to design ASICs or FPGAs.  BSV is based on a synthesizable subset of System Verilog, including System Verilog types, modules, module instantiation, interface instantiation, parameterization, static elaboration, and "generate" elaboration.  For product documentation and training material click here.