We are using the Cadence tools in academic research to design and layout SiGe Bipolar test circuits for 40 - 80 Gb/s data generation. The IBM SiGe 7HP process is the target process for this project. Interconnect group delay, clock and data distribution are being studied as well as the design of very high speed linear feedback shift registers and multiplexers.  Cadence tools are also being used in millimeter-wave communication circuits and high-speed serial link transceivers in 130-nm and 90-nm CMOS technology. The UMC 0.13-um logic process and the IBM CMOS 10SF are the target process. Specifically, we are designing T/R switches, low-noise amplifiers, power amplifiers and high-speed equalizers.