Identify RTL Debugger is the first software tool that allows you to probe and debug your FPGA design directly in the source RTL. You use Identify software to verify your design in hardware as you would in simulation – only much faster and with in-system stimulus.
The
Identify tool allows you to navigate your design graphically and mark
signals directly in RTL as probes or sample triggers. After synthesis,
you view the results in the RTL source code or in waveform. Design
iterations are rapidly done using incremental place and route. Identify
software is closely integrated with synthesis and routing tools for a
seamless development environment.
Synplify Premier
The Synplify Premier solution builds upon Synplicity's
industry-leading
synthesis technology and adds new graph-based physical synthesis and
real-time, simulator-like visibility into operating FPGA devices.
Graph-based physical synthesis provides rapid timing closure and up to
a 5-20% timing improvement.
Synplify DSP
Synplify DSP software is a true DSP synthesis tool and
the only one that performs high-level DSP optimizations from a Simulink
specification. These special DSP optimizations allow designers to
capture the behavior needed for their DSP algorithm without worrying
about the specific implementation in hardware. The Synplify DSP
solution automatically produces a highly optimized, technology
independent implementation of the design ready for RTL synthesis.
Certify
Certify ASIC prototyping solution is the leading product for ASIC prototyping using multiple FPGAs. Certify software combines RTL multi-chip partitioning with best-in-class FPGA synthesis. Using the Certify product makes ASIC prototyping significantly easier, shortens prototype development time, improves prototype performance, and enables faster time-to-market.