Rapid layout pattern classification

TitleRapid layout pattern classification
Publication TypeConference Paper
Year of Publication2011
AuthorsWuu, J-Y, Pikus, FG, Torres, A, Marek-Sadowska, M
Conference NameDesign Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific
Date Publishedjan.
KeywordsCD threshold, circuit analysis computing, fast physical verification tool, industrial designs, integrated circuit layout, layout object printability, pattern classification, pattern matching, pattern matching-based tools, rapid layout pattern classification, runtime enhancement techniques, size 32 nm, size 45 nm, support vector machines, two-level hotspot pattern classification methodology
AbstractPrintability of layout objects becomes increasingly dependent on neighboring shapes within a larger and larger context window. In this paper, we propose a two-level hotspot pattern classification methodology that examines both central and peripheral patterns. Accuracy and runtime enhancement techniques are proposed, making our detection methodology robust and efficient as a fast physical verification tool that can be applied during early design stages to large-scale designs. We position our method as an approximate detection solution, similar to pattern matching-based tools widely adopted by the industry. In addition, our analyses of classification results reveal that the majority of non-hotspots falsely predicted as hotspots have printed CD barely over the minimum allowable CD threshold. Our method is verified on several 45 nm and 32 nm industrial designs.