Publications

Found 231 results
2012
X. Qiu and M. Marek-Sadowska, “Can pin access limit the footprint scaling?”, in Proceedings of the 49th Annual Design Automation Conference, 2012, p. 1100–1106.
F. Chen, et al., “Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues”, in Reliability Physics Symposium (IRPS), 2012 IEEE International, 2012, p. 6A.4.1 -6A.4.9.
V. S. Nandakumar and M. Marek-Sadowska, “A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures”, Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, vol. 2, p. 266 -277, 2012.
X. Qiu, M. Marek-Sadowska, and W. Maly, “Vertical Slit Field Effect Transistor in ultra-low power applications”, in Quality Electronic Design (ISQED), 2012 13th International Symposium on, 2012, p. 384 -390.
2011
Yi-Wei Lin, M. Marek-Sadowska, and W. Maly, “On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 30, p. 229 -241, 2011.
J. - Y. Wuu, F. G. Pikus, M. Marek-Sadowska, and M. L. Rieger, “Efficient approach to early detection of lithographic hotspots using machine learning systems and pattern matching”, in Design for Manufacturability through Design-Process Integration V, 2011, vol. 7974.
V. S. Nandakumar and M. Marek-Sadowska, “Layout effects in fine grain 3D integrated regular microprocessor blocks”, in Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, 2011, p. 639 -644.
V. S. Nandakumar and M. Marek-Sadowska, “Low power, high throughput network-on-chip fabric for 3D multicore processors”, in Computer Design (ICCD), 2011 IEEE 29th International Conference on, 2011, p. 453 -454.
J. - Y. Wuu, F. G. Pikus, and M. Marek-Sadowska, “Metrics for characterizing machine learning-based hotspot detection methods”, in Quality Electronic Design (ISQED), 2011 12th International Symposium on, 2011, p. 1 -6.
M. Marek-Sadowska, “On old and new routing problems”, in ISPD '11: Proceedings of the 2011 international symposium on Physical design, 2011, p. 13–20.
Y. - S. Su, D. - C. Wang, S. - C. Chang, and M. Marek-Sadowska, “Performance Optimization Using Variable-Latency Design Style”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, p. 1874 -1883, 2011.
A. Todri and M. Marek-Sadowska, “Power Delivery for Multicore Systems”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, p. 2243 -2255, 2011.
J. - Y. Wuu, F. G. Pikus, A. Torres, and M. Marek-Sadowska, “Rapid layout pattern classification”, in Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific, 2011, p. 781 -786.
A. Todri and M. Marek-Sadowska, “Reliability Analysis and Optimization of Power-Gated ICs”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, p. 457 -468, 2011.
M. Marek-Sadowska and X. Qiu, “A study on cell-level routing for VeSFET circuits”, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, p. 127 -132.
W. Maly, et al., “Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration”, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, p. 145 -150.
Li, Di-an and M. Marek-Sadowska, “Variation-aware electromigration analysis of power/ground networks”, in Computer-Aided Design (ICCAD), 2011 IEEE/ACM International Conference on, 2011, p. 571 -576.
2010
Yi-Wei Lin, M. Marek-Sadowska, and W. Maly, “Layout Generator for Transistor-Level High-Density Regular Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 29, p. 197 -210, 2010.
Li, Di-an, M. Marek-Sadowska, and B. Lee, “On-chip em-sensitive interconnect structures”, in SLIP '10: Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction, 2010, p. 43–50.
Yi-Wei Lin, M. Marek-Sadowska, and W. Maly, “Performance study of VeSFET-based, high-density regular circuits”, in ISPD '10: Proceedings of the 19th international symposium on Physical design, 2010, p. 161–168.
V. S. Nandakumar, D. Newmark, Y. Zhan, and M. Marek-Sadowska, “Statistical static timing analysis flow for transistor level macros in a microprocessor”, in Quality Electronic Design (ISQED), 2010 11th International Symposium on, 2010, p. 163 -170.
2009
J. - Y. Wuu, F. G. Pikus, A. Torres, M. Marek-Sadowska, V. K. Singh, and M. L. Rieger, “Detecting context sensitive hot spots in standard cell libraries”, in Design for Manufacturability through Design-Process Integration III, 2009, vol. 7275, p. 727515.
A. Todri and M. Marek-Sadowska, “Electromigration study of power-gated grids”, in ISLPED '09: Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design, 2009, p. 315–318.
Y. - M. Kuo, Y. - T. Chang, S. - C. Chang, and M. Marek-Sadowska, “Spare Cells With Constant Insertion for Engineering Change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, p. 456 -460, 2009.
A. Todri, M. Marek-Sadowska, F. Maire, and C. Matheron, “A study of decoupling capacitor effectiveness in power and ground grid networks”, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009, p. 653 -658.

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