Integrated Photonics: From On-Chip Interconnects to Mars Communications

Photonic integrated circuits (PICs) have evolved over a period of more than 30 years from one-off devices realized with complex crystal growth steps to now foundry qualified circuits yielding high performance and wafer uniformity. This evolution was fostered by the maturation of compound semiconductor materials as well as the exploitation of already matured silicon manufacturing processes that were developed for the microelectronics industry. Although indium phosphide is the most mature photonic integration platform, a number of other technologies have emerged including silicon, silica, polymer, as well as heterogeneous platforms integrating more than one material. PICs reduce size, weight and power, and increase performance and reliability. Applications impacted by this technology include telecommunications, data center communications, high-performance computing, microwave photonics, fiber sensing, and bio sensing. This talk will describe several examples of high-performance PICs, novel materials for nanophotonic integrated circuits including graphene and indium tin oxide, and several new applications for integrated photonics including visible light and deep space communications.

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Learning Approaches to Analog and Mixed Signal Verification and Analysis

This work focus on addressing various problems related to the design automation of analog and mixed signal circuits. Analog circuits are typically highly specialized and fined tuned to fit the desired specifications for any given system reducing the reusability of circuits from design to design. This hinders the advancement of automating various aspects of analog design, test, and layout. At the core of many automation techniques, simulations or data collection are required. Unfortunately, for some complex analog circuits, a single simulation may take many days. This prohibits performing any type of behavior characterization or verification of the circuit. This leads us to the first fundamental problem with the automation of analog devices. How can we reduce the simulation cost while maintaining the robustness of transistor level simulations? As analog circuits can vary vastly from one design to the next and are hardly ever comprised of standard library based building blocks, the second fundamental question is how to create automated processes that are general enough to be applied to all or most circuit types? Finally, what circuit characteristics can we utilize to enhance the automation procedures?

Statistical learning techniques for improving the circuit verification efficiency is studied. To enable the application, circuit simulation is modeled as an event propagation process through a system consisting of primitive elements. Then, the efficiency improvements are achieved with two approaches. By assuming that the output space can be represented by a set of selected events, unsupervised learning is applied to search the input events that correspond to the selected output events. Only the selected input events are simulated, resulting in saving of the simulation time. During the simulation, low-complexity primitive elements with low information content are modeled by supervised learning models. Event propagation through these primitive elements is achieved by model prediction rather than by actual simulation, resulting in further saving of the simulation time. This chapter explains the statistical learning concepts and the techniques to implement the two approaches and demonstrates their effectiveness with experimental results in the context of voltage domain analysis of several analog circuit designs. The work is extended to provide critical node and environmental analysis of large analog and mixed signal systems.

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Photonic Technologies to Impact Future Systems: Efficiently Delivering and Routing Massive Bandwidth

The big opportunity for photonics is now Computercom: developing the interconnection networks that will underpin the next generations of high performance computers and data centers. Today, there are single machines with > 500,000 optical links. To enable tomorrow’s systems that will demand millions of links, interconnect technologies must be developed that simultaneously offer low cost, low-power consumption, and high bandwidth density. My talk will describe aggressive projects targeted at meeting this challenge, including the development of Tb/s parallel optical transceivers, VCSEL links that push the limits of speed and power efficiency, and highly-integrated Si photonic transceivers and switches. Beyond the development of enabling hardware, there are significant opportunities to exploit unique features of photonic technologies to gain application-level advantages for systems. In doing so, we hope to open new opportunities for the proliferation of optics beyond the traditional and ongoing replacement of copper.

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Realization and Formal Analysis of Asynchronous Pulse Communication Circuits

This work presents an approach to constructing asynchronous pulsed communication circuits. These circuits use small delay elements to introduce a gate-level sense of time, removing the need for either a clock, or a handshaking signal to be part of a high-speed communication link. This construction method allows the creation of links with better than normal jitter tolerance, allowing for simple circuit architectures that can easily be made robust to soft error.

A 5Gbps radiation-hardened link, targeted at use in detector modules at the LHC, will be presented. This application presents a special challenge due to both very high radiation levels (1MGy+ lifetime dose) and the demand for minimum material use. The presented link, realized in 130nm technology, is unique in that it is lower power (~50mW end to end) and lower area 0.12mm^2 including ESD protection and I/O amplifiers. Due to its asynchronous construction and the gate design style, the link essentially has no power dissipation when idle, and enters and exits its idle state with no delay.

In addition to the construction of the link, this presentation covers the design and analysis methodology that can be used to create communication components attached to the link. The methodology used to construct the serializer, deserializer, and self-test circuitry for the link has the capacity to create fast logic circuits. In this case, a 5Gbps SER/DES and a 2GHz RNG are implemented in 130nm CMOS technology using a gate design style that does not dissipate static power.

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ECE Professor Kaustav Banerjee elected as a Fellow of the American Physical Society (APS)

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Banerjee elected for “seminal applied physics research on nanoscale materials, devices, interconnects, and circuits towards realizing ultra-low power electronics.”

The criterion for election as an APS Fellow is exceptional contributions to the physics enterprise; e.g., outstanding physics research, important applications of physics, leadership in or service to physics, or significant contributions to physics education. Fellowship is a distinct honor signifying recognition by one’s professional peers.

The membership of APS is diverse and global, and the Fellows of the APS should reflect that diversity. Fellowship nominations of women, members of underrepresented minority groups, and scientists from outside the United States are especially encouraged.

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Phase-sensitive Optical Parametric Amplifiers in Optical Fiber Transmission

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A review of recent advances of the use of phase-sensitive amplifiers (PSAs) in optical transmission links is provided. These amplifiers not only amplify light with lowest possible noise figure (0 dB quantum limit, 1 dB reported) but can also mitigate the transmission fiber nonlinear impairment, a result of the coherent superposition of the signal and idler waves in the amplifier.

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Topics in Modeling and Control of Spatially Distributed Systems

This dissertation consists of three parts centered around the topic of spatially distributed systems.

The first part treats a specific spatially distributed system, the so-called Rijke tube, an experiment illustrating the unstable interplay of heat exchange and gas dynamics. The experiment is described and it is demonstrated how closed-loop system identification tools can be applied to obtain a transfer function model, before a spatially distributed model is developed and analyzed. The model in its most idealized form can be described in the frequency domain by a matrix of non-rational transfer functions, which facilitates analysis with classical methods such as the root locus.

The second part considers the following problem: for a given plant and cost function, could there be a finite-length periodic trajectory that achieves better performance than the optimal steady state? Termed optimal periodic control (OPC), this problem has received attention over several decades, however most available methods employ state-space based methods and hence scale very badly with plant dimension. Here, the problem is approached from a frequency-domain perspective, and methods whose complexity is independent of system dimension are developed by recasting the OPC problem for linear plants with certain memoryless polynomial nonlinearities as the problem of minimizing a polynomial.

Finally, the third part extends results for a special class within spatially distributed systems, that of spatially invariant systems, from systems defined on spaces of square-integrable functions to systems whose state space is an inner-product Sobolev space as they arise when considering systems of higher temporal order. It is shown how standard results on exponential stability, stabilizability and LQ control can be generalized by carefully keeping track of spatial frequency weighting functions related to the Sobolev inner products, and simple recipes for doing so are given.

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ECE Professor Yuan Xie named as an Institute of Electrical and Electronics Engineers (IEEE) Fellow

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Xie elected for his for contributions to design automation and architecture of three-dimensional integrated circuits

Yuan Xie, Professor of ECE department, University of California, Santa Barbara, has been named an IEEE Fellow (class of 2015, effective 1 January 2015). He is being recognized for contributions to design automation and architecture of three-dimensional integrated circuits (3D ICs).

The IEEE Grade of Fellow is conferred by the IEEE Board of Directors upon a person with an outstanding record of accomplishments in any of the IEEE fields of interest. The total number selected in any one year cannot exceed one-tenth of one- percent of the total voting membership. IEEE Fellow is the highest grade of membership and is recognized by the technical community as a prestigious honor and an important career achievement.

Professor Xie is recognized as the world-class researcher in the areas of electronic design automation (EDA), computer architecture, VLSI design, and embedded systems. His most distinctive contributions lie in the revolutionary advances of design automation and architecture for three-dimensional integrated circuits (3D ICs), which offer new opportunities for system-level innovations that are not hinged only on technology scaling. He is recognized as the pioneer who have crossed traditional boundaries between architecture, design automation, and test for 3D ICs, and his cross-cutting research have made significant contributions to transform this emerging technology from research exploration to commercial adoption in semiconductor industry.

Prof Xie received BS degree and Ph.D. degree from Tsinghua University and Princeton University, respectively. He has worked for IBM and AMD, and was with Pennsylvania State University before joining UCSB in Fall 2014. He has published more than 200 scholarly articles in top journal and conference venues, and has received several Best Paper Awards (ICCAD, ASPDAC, ISLPED, ISVLSI, GLSVLSI) and several Best Paper Nominations (MICRO, HPCA, DATE, ASPDAC).

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PhD Defense: “Scalable Front End Designs for Communication and Learning”

In this talk, we consider three classical estimation and detection problems that face new scalability challenges. We discuss front end designs which are customized to the specific application at hand and make the systems more scalable and efficient. The first two case studies pertain to the canonical problems of synchronization and equalization for communication links. As the system bandwidths scale, challenges arise due to the limiting resolution of analog-to-digital converters (ADCs). We discuss new architectures that react to this bottleneck by drastically relaxing the precision requirements of the front end and appropriately adapting the back end algorithms using Bayesian principles. We demonstrate the importance of using a dither prior to quantization and carefully designing the quantization thresholds. The third problem we discuss belongs to the field of computer vision. Inspired by the research in neuroscience about the mammalian visual system, we redesign the front end of a machine vision system to be neuro-mimetic, followed by layers of unsupervised learning using k-means clustering. This results in a framework that is intuitive, easier to implement compared to the approach of supervised deep networks, and amenable to the increasing availability of large amounts of unlabeled data. Supervised classification, using a generic support vector machine (SVM), is applied at the end. We obtain competitive classification results on standard image databases NORB and MNIST.

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Probabilistic Graphical Models for Contour Tracking and Segmentation in Electron Microscopy Images

Automatic 3D reconstruction of neuronal circuitry in biological images is key to discerning cellular ultra structure. This talk covers my research work on the problem of 3D reconstruction of neuronal cells in electron microscopy images, using probabilistic graphical models. First I will cover a 1D hidden Markov model-based contour tracking algorithm for a single or a few neuronal processes involving topological changes. In this method, uncertain segments with lower likelihoods are detected, and then a few hypothetical arcs are created to perform contour refinement to enable the discovery and corresponding tracing of topology changes. Secondly I will cover a method, wherein a two-dimensional hidden Markov model is utilized for tracing a large number of cells by modeling the problem as a pixel labeling task. This method leverages the concept of spatially adaptive states, wherein the state-space at each pixel is locally extracted to be a small subset of the full state-space. This local adaptation of states, not only reduces the computational complexity significantly, but also improves the segmentation accuracy. While the first contour tracking algorithm precisely locates cell boundaries, the second pixel-labeling-based algorithm easily scales to a large number of cells, and hence represent two complimentary techniques that together offer significant advancement on the problem of 3D reconstruction of neuronal cells.

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