Model { Name "id_p3_mod" Version 5.0 SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ExecutionOrder off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Sat Jan 24 13:15:49 2004" Creator "hespanha" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "tomde" ModifiedDateFormat "%" LastModifiedDate "Mon Mar 15 23:47:54 2004" ModelVersionFormat "1.%" ConfigurationManager "None" SimParamPage "Solver" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeMexFile "ext_comm" ExtModeBatchMode off ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock off BufferReuse on RTWExpressionDepthLimit 5 SimulationMode "normal" Solver "ode5" SolverMode "Auto" StartTime "0.0" StopTime "10.0" MaxOrder 5 MaxStep "auto" MinStep "auto" MaxNumMinSteps "-1" InitialStep "auto" FixedStep "sample" RelTol "1e-3" AbsTol "auto" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" LoadExternalInput off ExternalInput "[t, u]" LoadInitialState off InitialState "xInitial" SaveTime on TimeSaveName "tout" SaveState off StateSaveName "xout" SaveOutput on OutputSaveName "yout" SaveFinalState off FinalStateName "xFinal" SaveFormat "Array" Decimation "1" LimitDataPoints on MaxDataPoints "1000" SignalLoggingName "sigsOut" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" CheckForMatrixSingularity "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SfunCompatibilityCheckMsg "none" RTWInlineParameters off BlockReductionOpt on BooleanDataType on ConditionallyExecuteInputs on ParameterPooling on OptimizeBlockIOStorage on ZeroCross on AssertionControl "UseLocalSettings" ProdHWDeviceType "Microprocessor" ProdHWWordLengths "8,16,32,32" RTWSystemTargetFile "grt.tlc" RTWTemplateMakefile "grt_default_tmf" RTWMakeCommand "make_rtw" RTWGenerateCodeOnly off RTWRetainRTWFile off TLCProfiler off TLCDebug off TLCCoverage off TLCAssertion off BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType Clock DisplayTime off } Block { BlockType Fcn Expr "sin(u[1])" } Block { BlockType Integrator ExternalReset "none" InitialConditionSource "internal" InitialCondition "0" LimitOutput off UpperSaturationLimit "inf" LowerSaturationLimit "-inf" ShowSaturationPort off ShowStatePort off AbsoluteTolerance "auto" ZeroCross on } Block { BlockType RandomNumber Mean "0" Variance "1" Seed "0" SampleTime "-1" VectorParams1D on } Block { BlockType Step Time "1" Before "0" After "1" SampleTime "-1" VectorParams1D on ZeroCross on } Block { BlockType Sum IconShape "rectangular" Inputs "++" ShowAdditionalParam off InputSameDT on OutDataTypeMode "Same as first input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on } Block { BlockType ToWorkspace VariableName "simulink_output" MaxDataPoints "1000" Decimation "1" SampleTime "0" } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "id_p3_mod" Location [2, 82, 1014, 722] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" ReportName "simulink-default.rpt" Block { BlockType Clock Name "Clock" Position [320, 80, 340, 100] Decimation "10" } Block { BlockType Fcn Name "Fcn" Position [230, 180, 290, 210] Orientation "down" NamePlacement "alternate" Expr "-u(1)-(u(1))^3" } Block { BlockType Integrator Name "Integrator" Ports [1, 1] Position [340, 130, 370, 160] Orientation "left" Port { PortNumber 1 Name "x1" TestPoint off LinearAnalysisOutput off LinearAnalysisInput off RTWStorageClass "Auto" DataLogging off DataLoggingNameMode "SignalName" DataLoggingDecimateData off DataLoggingDecimation "2" DataLoggingLimitDataPoints off DataLoggingMaxPoints "5000" } } Block { BlockType Integrator Name "Integrator1" Ports [1, 1] Position [345, 245, 375, 275] Port { PortNumber 1 Name "x2" TestPoint off LinearAnalysisOutput off LinearAnalysisInput off RTWStorageClass "Auto" DataLogging off DataLoggingNameMode "SignalName" DataLoggingDecimateData off DataLoggingDecimation "2" DataLoggingLimitDataPoints off DataLoggingMaxPoints "5000" } } Block { BlockType RandomNumber Name "Random\nNumber" Position [260, 95, 290, 125] Orientation "left" NamePlacement "alternate" Variance "noise" SampleTime "0" } Block { BlockType Step Name "Step" Position [80, 265, 110, 295] After "step_mag" SampleTime "0" Port { PortNumber 1 Name "u" TestPoint off LinearAnalysisOutput off LinearAnalysisInput off RTWStorageClass "Auto" DataLogging off DataLoggingNameMode "SignalName" DataLoggingDecimateData off DataLoggingDecimation "2" DataLoggingLimitDataPoints off DataLoggingMaxPoints "5000" } } Block { BlockType Sum Name "Sum" Ports [2, 1] Position [275, 232, 305, 288] NamePlacement "alternate" ShowName off Inputs "|++" InputSameDT off OutDataTypeMode "Inherit via internal rule" } Block { BlockType Sum Name "Sum1" Ports [2, 1] Position [190, 117, 215, 173] Orientation "left" ShowName off Inputs "|++" InputSameDT off OutDataTypeMode "Inherit via internal rule" } Block { BlockType ToWorkspace Name "T Workspace2" Position [65, 75, 125, 105] Orientation "left" NamePlacement "alternate" ShowName off VariableName "noise" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace" Position [65, 130, 125, 160] Orientation "left" ShowName off VariableName "x1" MaxDataPoints "inf" SampleTime "sample" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace1" Position [65, 180, 125, 210] Orientation "left" ShowName off VariableName "u" MaxDataPoints "inf" SampleTime "sample" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace2" Position [385, 75, 445, 105] NamePlacement "alternate" ShowName off VariableName "t" MaxDataPoints "inf" SampleTime "sample" SaveFormat "Array" } Line { SrcBlock "Sum1" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Random\nNumber" SrcPort 1 Points [-20, 0] Branch { Points [0, -20] DstBlock "T Workspace2" DstPort 1 } Branch { Points [0, 35] DstBlock "Sum1" DstPort 1 } } Line { Name "u" Labels [0, 0] SrcBlock "Step" SrcPort 1 Points [135, 0] Branch { DstBlock "Sum" DstPort 2 } Branch { Labels [2, 0] Points [-50, 0; 0, -85] DstBlock "To Workspace1" DstPort 1 } } Line { SrcBlock "Fcn" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "Sum" SrcPort 1 DstBlock "Integrator1" DstPort 1 } Line { Name "x1" Labels [0, 0] SrcBlock "Integrator" SrcPort 1 Points [-75, 0] Branch { DstBlock "Fcn" DstPort 1 } Branch { Points [-15, 0; 0, 20] DstBlock "Sum1" DstPort 2 } } Line { Name "x2" Labels [0, 0] SrcBlock "Integrator1" SrcPort 1 Points [70, 0; 0, -115] DstBlock "Integrator" DstPort 1 } Line { SrcBlock "Clock" SrcPort 1 DstBlock "To Workspace2" DstPort 1 } } }