The originally planned HW6, intended to cover chapters 15-16, was merged into HW5 to allow solutions to be provided and discussed before Midterm 2. The following (last homework assignment for the course) was HW7 in the syllabus distributed at the start of the winter term.

Do the following problems from the textbook: 17.5 [15 pts], 18.5bd [20 pts], 18.11 [20 pts], 19.4 [20 pts], 20.1b [10 pts], 20.12a [15 pts]

Suggested problems (ch. 21-24, for practice only, not to be turned in)

Do the following problems from the textbook: 21.8, 21.9 [Correction: Example 21.2 is intended], 22.1, 22.5, 22.9, 23.4, 24.2, 24.11

Grade stats

Pretest Grades -- Prob. 1: Range = [0, 100], Median = 50, Mean = 45, SD = 31; Prob. 2: Range = [0, 100], Median = 50, Mean = 52, SD = 24; Prob. 3: Range = [0, 100], Median = 50, Mean = 60, SD = 28; Prob. 4: Range = [0, 100], Median = 50, Mean = 44, SD = 29.

HW1 Grades: Range = [35, 99], Median = 85, Mean = 81, SD = 14

HW2 Grades: Range = [57, 100], Median = 77, Mean = 81, SD = 12

HW3 Grades: Range = [42, 93], Median = 85, Mean = 82, SD = 10

HW4 Grades: Range = [12, 100], Median = 75, Mean = 71, SD = 20

HW5 Grades: Range = [25, 100], Median = 83, Mean = 79, SD = 16

HW6 Grades: Range = [52, 93], Median = 75, Mean = 75, SD = 11

MT1 Grades: Range = [29, 87], Median = 60, Mean = 59, SD = 14

MT2 Grades: Range = [52, 98], Median = 78, Mean = 77, SD = 11

Final Exam Grades: Range = [27, 93], Median = 67, Mean = 66, SD = 13

Sample Midterm Exam

The following is meant to indicate the types and levels of problems in the midterm, rather than the coverage (which is outlined in the lecture schedule and below). This particular exam covered up to the end of Chapter 12 of the textbook and was 105 minutes long (our two midterms will be 75 minutes each). Table 6.2 of the text was appended to the end of the exam for reference in solving Problem 3.

Problem 1 [15 points]. Defining concepts and terms -- Define each of the following concepts/terms precisely and concisely within the space provided (about 1.5 inch per term) [3 points each]: Decoder; PC-relative addressing; Pseudoinstruction; Assembler directive; Directed rounding.

Problem 2 [25 points]. Amdahl's law -- Problem 4.16 in the text [part a, 15 points; part b, 10 points]

Problem 3 [20 points] Machine instructions -- Problem 7.3 in the text, parts d and g [10 points each]

Problem 4 [20 points] Multifunction ALU -- Consider the following multifunction ALU studied in class. Specify the control signal values that are needed for executing the following two instructions. [10 points each]  [Fig. 10.19 of the text goes here] (a) sll. (b) slt.

Problem 5 [20 points] Shift-add binary hardware multiplier -- In the following diagram of a radix-2 hardware multiplier, explain: [Fig. 11.4 of the text goes here] (a) [6 points] Why the register holding the multiplier y can be merged with the one holding the doublewidth partial product z^(j). (b) [6 points] The role of the multiplexer. (c) [8 points] How separate cycles or phases for loading the doublewidth partial product register and shifting it to the right can be avoided.

Sample Final Exam

The following is meant to indicate the types and levels of problems in the final, rather than the coverage (which is outlined in the lecture schedule and below). This particular exam covered up to the end of Chapter 24 of the textbook and was 150 minutes long. The single midterm had included up to the end of Chapter 12 in the textbook.

Problem 1 [16 points]. Defining concepts and terms -- Define each of the following concepts/terms precisely and concisely within the space provided (about 1 inch per term) [2 points each]: Bus arbitration; Conflict miss; Delayed branch; Interrupt handler; Pseudoinstruction; Set-associative cache; TLB.

Problem 2 [15 points] Computer arithmetic -- Problem 11.10a in the text.

Problem 3 [12 points] Processor data path -- Problem 13.2b in the text.

Problem 4 [16 points] Control unit design -- The following diagram shows a microprogrammed implementation of control unit functions [Fig. 14.7 of the text goes here]. (a) Does this diagram represent a single-cycle or multicycle implementation? Why? (b) What are the roles of the dispatch ROMs? (c) How are the values of the "Sequence control" signals, that control the 4-input mux, decided? (d) Name and describe two of the control signals that go from the microinstruction register to the data path section (choose any two and describe their functions briefly).

Problem 5 [15 points] Pipelining -- In the following diagram, a pipelined data path for MicroMIPS and some of its controls are shown [Fig. 15.10 of the text goes here]. Explain the roles of: (a) The control signals that are stored in the bottom part of the pipeline registers. (b) The multiplexer that appears below the SE circle, next to the register file. (c) The multiplexer located above the program counter.

Problem 6 [16 points] Memory hierarchy -- Example 20.3 in the text.

Problem 7 [10 points] Input/Output -- Example 22.5 in the text.

Midterm and Final Exam Preparation

The following includes topics that will be emphasized, as well as list of exclusions from the midterm exams (Chapters 4-10 for midterm 1, Chapters 13-16 for midterm 2) and final exam (Chapters 4-24). All sections not specifically excluded are required, even if they are not covered in class.

Chapters 1-3 -- No direct problem or question, but you need to know (and be able to define) concepts such as tristate buffers, multiplexers, register files, and so on, used to explain the topics that follow.

Chapter 4 -- Computer performance: problem likely on CPI calculation, performance enhancement (Amdahl's law), instruction mix, and/or benchmarks.

Chapters 5-8 -- Instruction-set architecture: You do not need to memorize instruction codes or formats. Any problem in this area will be accompanied by a reference table providing a list of codes and formats if required. Ignore Sections 7.5, 7.6, and 8.4.

Chapters 9-10 -- Computer arithmetic: problem likely on 2's-complement numbers, number radix conversion, floating-point number formats, shift/logical operations (including distinction between arithmetic and logical shifts), adders and ALUs.

Chapters 13-14 -- Data path and control: problem very likely on control unit structure, control signal generation, multicycle instruction execution, and control state machine. Section 14.5 is excluded.

Chapter 15-16 -- Pipelining: problem very likely on pipeline bubbles (how to insert or avoid them), pipeline control, data hazards, data forwarding, control hazards, delayed branch, and/or branch prediction.

The following apply to the final exam, which will include material from the preceding chapters as well, but to a lesser degree.

Chapters 17-20 -- Memory hierarchy: problem very likely on the need for memory hierarchy, cache memory concepts (levels 1 and 2), miss/hit rate, average memory access time, compulsory/capacity/conflict misses, mapping schemes, virtual memory, page table, and/or TLB. Sections 17.5, 19.5, and 19.6 are excluded.

Chapters 21-24 -- Input/output and interfacing: problem possible on memory-mapped, polled, or interrupt-driven I/O, buses, and interrupts. Sections 21.5, 21.6, 22.6, 23.5, 23.6, 24.5, and 24.6 are excluded.

Chapters 25-28 -- Advanced architectures: no problem or question.  

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