Page last updated on 2014 August 22

*Enrollment code:* Depends on the discussion session chosen

*Prerequisite:* ECE 152A or equivalent

*Class meetings:* TR 2:00-3:15, Psych 1902

*Discussion option 1:* F 09:00-09:50 (TA1, code 13698), Phelps 1508

*Discussion option 2:* F 10:00-10:50 (TA2, code 13714), Phelps 3523

*Discussion option 3:* F 11:00-11:50 (TA3, code 13706), NH 1109

*Instructor:* Professor Behrooz Parhami

*Teaching assistant 1:* TBD, TBD at umail.ucsb.edu

*Teaching assistant 2:* TBD, TBD at umail.ucsb.edu

*Teaching assistant 3:* TBD, TBD at umail.ucsb.edu

*Intructor's office hours:* M 3:00-4:30, W 12:30-2:00, HFH 5155

*TA office hours:* TBD (TA1), TBD (TA2), TBD (TA3), TBD location

**Course announcements:** Listed in reverse chronological order

**Course calendar:** Schedule of lectures, assignments, and exams

**Homework assignments:** Three assignments, worth a total of 15%

**Practical projects:** Two projects, worth a total of 20%

**Exams:** Midterm (25%) and final (40%), both closed-book

**Policy on academic integrity:** Please read very carefully

**Grade statistics:** Range, mean, etc. for assignment/exam grades

**References:** Textbook and other info sources (Textbook's web page)

**Lecture slides:** Available on the textbook's web page

**Miscellaneous information:** Motivation, catalog entry, history

**2014/07/14:** Welcome to the ECE 154A Web site for fall 2014. The following information is tentative and is provided for planning purposes only. The course lecture schedule and requirements will be finalized in late September 2014, with updates appearing at least weekly thereafter. Major changes and additions to the page content will be outlined in this announcements area.

Course lectures, homework assignments, practical projects, and exams are scheduled as follows. This schedule will be strictly observed. While not mandatory, class attendance helps in identifying important topics and compiling a study guide, particularly if the material covered in each lecture are studied or at least browsed beforehand. PowerPoint and pdf files of course lectures can be found on the Textbook's web page.

**Day & Date (book chapters) Lecture/discussion topic [Homework posted/due] {Special notes}**

R 10/02 (ch. 1) Course introduction, review of combinational logic circuits

F 10/03 (ch. 1-2) Discussion on logic circuits

T 10/07 (ch. 2) Review of sequential logic circuits and registers [Homework 1 posted, ch. 1-4]

R 10/09 (ch. 3) Computer technology overview

F 10/10 (ch. 1-3) Discussion on computer hardware; Project 1 preview

T 10/14 (ch. 4) Introduction to computer performance

R 10/16 (ch. 5) MiniMIPS instructions and addressing modes [Project 1 posted, ch. 5-8]

F 10/17 (ch. 4) Discussion on computer performance and HW1 [Homework 1 due]

T 10/21 (ch. 6) MiniMIPS additional instructions

R 10/23 (ch. 7-8) Assembly programs and ISA variations

F 10/24 (ch. 5-8) Discussion on instruction-set architecture and Project 1

T 10/28 (ch. 9) Number representation [Homework 2 posted, ch. 9-12]

R 10/30 (ch. 10) Addition circuits and simple ALUs

F 10/31 (ch. 9-10) Discussion on number representation, addition, and ALUs [Project 1 due]

T 11/04 (ch. 11) Multiplication and division

R 11/06 (ch. 12) Floating-point arithmetic

F 11/07 (ch. 11-12) Discussion on computer arithmetic and HW2 [Homework 2 due]

T 11/11 Veterans Day Holiday: No lecture

R 11/13 (ch. 1-12) Midterm exam, in our regular classroom (closed-book)

F 11/14 Discussion on midterm exam

T 11/18 (ch. 13) Stages of instruction execution [Project 2 posted, ch. 13-15]

R 11/20 (ch. 14) Control unit synthesis

F 11/21 (ch. 13-14) Discussion on data path and control

T 11/25 (ch. 15) Basics of pipelined data paths

R 11/27 Thanksgiving holiday: no lecture

F 11/28 Thanksgiving weekend: no discussion sessions

T 12/02 (ch. 16) Advanced pipelining and performance limit [Homework 3 posted, ch. 16-19]

R 12/04 (ch. 17, 19) Main and mass memory concepts

F 12/05 (ch. 15-16) Pipelined data paths and their performance implications [Project 2 due]

T 12/09 (ch. 18) Cache memories

R 12/11 (ch. 4, 16, 18) Computer performance revisited

F 12/12 (ch. 4, 16-19) Discussion on memory, performance, and HW3 [Homework 3 due]

T 12/16 (ch. 1-19) Final exam, 4:00-7:00 PM, in our regular classroom (closed-book)

T 12/23 {Grades to be submitted by midnight}

-Deposit solutions in ECE 154 homework box (3120 HFH) before 10:00 AM on due date.

-Because solutions will be handed out on the due date, no extension can be granted.

-Use a cover page that includes your name, course name, and assignment number.

-Staple the sheets and write your name on top of each sheet in case they are separated.

-Some cooperation is permitted, but direct copying of work will have severe consequences.

** Homework 1: Computer technology and performance** (ch. 1-4, due F 10/17, 10:00 AM)

Do these problems from the textbook: TBD

** Homework 2: Computer arithmetic** (ch. 9-12, due F 11/07, 10:00 AM)

Do these problems from the textbook: TBD

** Homework 3: Pipelining and memory** (ch. 16-19, due F 12/12, 10:00 AM)

Do these problems from the textbook: TBD

Project specifications, documentation requirements, and submission procedure will appear here when available. Projects are assigned to each student and must be performed individually and independently. Rules of academic honesty apply to projects just like homework assignments and exams. Please begin work on assigned project early, as no extension to the deadline will be granted.

** Project 1: Assembly language programming** (ch. 5-8, due F 10/31, 10:00 AM)

Project description: TBD

** Project 2: Program instrumentation and performance** (ch. 13-15, due F 12/05, 10:00 AM)

Project description: TBD

The following sample exams are meant to indicate the types and levels of problems, rather than the coverage (which is outlined in the course calendar). Students must study any section or topic that is not specifically excluded in the study guide that follows the sample exams, even if the material was not covered in class lectures. The final exam will also cover the midterm material, but to a lesser degree.

*Sample Midterm 1*

Problem 1 [15 points]. Defining concepts and terms -- Define each of the following concepts/terms precisely and concisely within the space provided (about 1.5 inches per term) [3 points each]: Decoder; PC-relative addressing; Pseudoinstruction; Assembler directive; Biased number representation.

Problem 2 [25 points]: Problem 4.4 in the textbook.

Problem 3 [15 points]: Problem 4.6a in the textbook.

Problem 4 [20 points]: Can you replace the following sequence of MiniMIPS instructions with fewer instructions, without changing the functionality? Explain your answer fully. Assume that the values computed in $t0 and $t1 are temporaries that are not needed elsewhere in the program (Table 6.2 will be provided as reference with problems such as this one):

and $t0,$s0,$s1

or $t1,$s1,$s0

beq $t0,$t1,label

Problem 5 [25 points]: In Fig. 10.19 (provided), explain each of the following:

a. Why the overflow signal is formed by an XOR gate.

b. The role of the *k* XOR gates on the input side of the adder.

c. The total number of control signals supplied to the ALU (show how computed).

d. Why the shifter and logic unit are likely to be faster than the adder.

*Sample Midterm 2*

Problem 1 [20 points]. Defining concepts and terms -- Define each of the following concepts/terms precisely and concisely within the space provided (about 1.5 inches per term) [4 points each]: Data forwarding; Loop unrolling; Microprogramming, Optimal pipelining; Pipeline data dependency.

Problem 2 [20 points]: Problem 13.1a in the textbook.

Problem 3 [20 points]: Problem 14.12a in the textbook.

Problem 4 [20 points]: Problem 15.2 in the textbook.

Problem 5 [20 points]: Problem 16.2 in the textbook.

*Sample Final Exam*

Problem 1 [10 points]. Defining concepts and terms -- Define each of the following concepts/terms precisely and concisely within the space provided (about 1.5 inches per term) [2 points each]: Bus arbitration; Conflict miss; Delayed branch; Set-associative cache; TLB

Problem 2 [15 points]: Problem 4.7 in the textbook.

Problem 3 [15 points]: Problem 11.5 in the textbook.

Problem 4 [15 points]: Problem 14.2c in the textbook.

Problem 5 [15 points]: Problem 16.9ab in the textbook.

Problem 6 [15 points]: Problem 18.3c in the textbook.

Problem 7 [15 points]: Problem 20.4a in the textbook.

*Midterm and Final Exam Study Guide**The following includes topics that will be emphasized in the course exams, as well as excluded topics. *

[Chapters 1-3] No direct problem or question, but you need to know (and be able to define) concepts such as tristate buffers, multiplexers, register files, and so on, used to explain the topics that follow.

[Chapter 4] Computer performance: Problem likely on CPI calculation, performance enhancement (Amdahl's law), instruction mix, and/or benchmarks.

[Chapters 5-8] Instruction-set architecture: You do not need to memorize instruction codes or formats. Any problem in this area will be accompanied by a reference table providing a list of codes and formats if required. Ignore Sections 7.5, 7.6, and 8.4.

[Chapters 9-11] Computer arithmetic: Problem likely on 2's-complement numbers, number radix conversion, floating-point number formats, shift/logical operations (including distinction between arithmetic and logical shifts), adders and ALUs, basics of multipliers.

[Chapters 13-14] Data path and control: Problem very likely on control unit structure, control signal generation, multicycle instruction execution, and control state machine. Section 14.5 is excluded.

[Chapter 15-16] Pipelining: Problem very likely on pipeline bubbles (how to insert or avoid them), pipeline control, data hazards, data forwarding, control hazards, delayed branch, and/or branch prediction.

[Chapters 17-19] Memory system: Problem very likely on the need for memory hierarchy, cache memory concepts (levels 1 and 2), miss/hit rate, average memory access time, compulsory/capacity/conflict misses, mapping schemes. Sections 17.5, 19.5, and 19.6 are excluded.

[Chapters 20-28] Virtual memory, I/O, interfacing, Advanced architectures: No problem or question.

*Grades listed are in percent, unless otherwise noted*.

Homework 1 grades: Range = [00, 00], Mean = 00, SD = 00, Median = 00

Homework 2 grades: Range = [00, 00], Mean = 00, SD = 00, Median = 00

Homework 3 grades: Range = [00, 00], Mean = 00, SD = 00, Median = 00

Project 1 grades: Range = [00, 00], Mean = 00, SD = 00, Median = 00

Project 2 grades: Range = [00, 00], Mean = 00, SD = 00, Median = 00

Midterm exam grades: Range = [00, 00], Mean = 00, SD = 00, Median = 00

Final exam grades: Range = [00, 00], Mean = 00, SD = 00, Median = 00

** Required text:** B. Parhami,

W. Stallings,

** Motivation:** Computer architecture is the study/specification of (digital) computer systems at the interface of hardware and software. Computer architecture is driven from the software side by user needs in terms of functions and speed and from the hardware side by technological innovations and constraints. ECE 154A introduces you to this exciting field and makes you an informed computer user who understands basic architectural features as well as their cost/performance implications. The programmer's view of the instruction set and user interface are considered along with memory organization, addressing methods, and performance parameters. By taking ECE 154B, you will learn additional topics such as input/output, buses, interfacing, and a multitude of performance issues and computation speedup methods. ECE 154A/B prepare you for participation in computer design efforts and for learning the advanced implementation methods and technologies used in high-performance uniprocessors (ECE 254A), parallel processors (ECE 254B), and distributed systems (ECE 254C).

** Catalog entry: ECE 154A. Introduction to Computer Architecture.** (4) PARHAMI.

Instruction-set architecture (ISA) and computer performance; Machine instructions, assembly, addressing modes; Memory map, arrays, pointers; Procedure calls; Number formats; Simple ALUs; Data path, control, microprogram; Buses, I/O programming, interrupts; Pipelined data paths and control schemes.

** History:** Computer architecture is a required subject in the Computer Engineering Program, and it can be taken as an optional subject by students in certain other majors. In 2013, the course ECE 154 (Introduction to Computer Architecture) was merged with the discontinued ECE 15B to form the ECE 154A/B sequence, dubbed introductory and advanced computer architecture. The computer architecture course offered by the Computer Science Department, CMPSC 154, was equivalent to ECE 154 many years ago, but the two courses have diverged in content to serve the needs of different curriula and student populations. The following record of previous offerings includes only those taught by Professor Parhami.

Offering of ECE 154 in winter 2011 (PDF file)

Offering of ECE 154 in winter 2010 (PDF file)

Offering of ECE 154 in winter 2009 (PDF file)

Offerings of ECE 154 from 2000 to 2008 (PDF file)