ECE152A's Homepage
Catalog Description
Design of synchronous digital systems: timing diagrams, propagation delay, latches and flipflops,
shift registers and counters, Mealy/Moore finite state machines, Verilog, 2-phase
clocking, timing analysis, CMOS implementation, S-RAM, RAM-based designs, ASM charts, state
minimization.
Lecture Topics
- Introduction to Digital Logic
- Boolean Algebra, Karnaugh Maps
- Multi-level Gate Circuits, Combinational Circuits and PLAs
- Basics of Verilog Coding
- Latches
- Flip-Flops
- Registers
- Counter Design
- State Graphs and Tables
- Reduction of State Tables
- State Assignment
- Sequential Circuit Design
- Moore and Mealy Machines
- Arithmetic Circuits
- RAM and ROM Based Digital Design
- State Machine Charts
Four labs: Implemented on an FPGA board, require verilog knowledge.
Text Book: Fundamentals of Logic Design, Roth and Kinney, Cengage Learning.
All course material is available on Canvas
