PUBLICATIONS

Most of the papers are copyrighted by ACM or IEEE. They are posted here for your personal use, to ensure timely dissemination of research work with no commercial purpose.

20xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Click here to DOWNLOAD PDF FILES FOR FREE for all papers enabled by ACM Author-Izer service

.
For other papers listed below but not included in ACM digital library, I will add links to PDF as soon as possible. Or you may email me for a copy of PDF file.

Journal Publications

  • [J1].Zhe Wang, Shuchang Shan, Ting Cao, Junli Gu, Yi Xu, Yuan Xie, Daniel Jimenez."WADE: Writeback-AwareDynamic Cache Management for NVM-based Main Memory System." To appear in ACM Transactions on Architecture andCode Optimization (TACO)

  • [J2]. Wulong Liu, Yu Wang, Yuchun Man, Huangzhong Yang, Yuan Xie. "On-Chip Hybrid Power Supply System for WirelessSensor Nodes" To Appear in ACM Journal of Emerging Technologies in Computing Systems (JETC)., 2014.

  • [J3]. Xiangyu Dong, Norm Jouppi, Yuan Xie. "A Circuit-Architecture Co-optimization Framework for Exploring Non-volatileMemory Hierarchies." ACM Transactions on Architecture and Code Optimization (TACO), Vol. 10, No. 4, 12/2013

  • [J4]. Xiaoming Chen, Yu Wang, Yu Cao, Yuan Xie, Huazhong Yang. "Assessment of Circuit Optimization Techniques underNBTI." To Appear in IEEE Computer Design and Test, 2013

  • [J5]. Jishen Zhao, Guangyu Sun, Gabriel Loh, Yuan Xie."Optimizing GPU Energy Efficiency with In-Package GraphicsMemory and Reconfigurable Memory Interface." ACM Transactions on Architecture and Code Optimization (TACO), Vol.10, No. 4, 12/2013

  • [J6]. Yibo Chen, Eren Kursun, Dave Motschman, Charles Johnson, Yuan Xie. "Through Silicon Via aware Design Planningfor Thermally-efficient 3D Integrated Circuits " IEEE Transactions on Computer Aids Design (TCAD)., pp.1335-1346, Vol.32, No. 9, Sept. 2013.

  • [J7]. Xiangyu Dong, Cong Xu, Yuan Xie, Norm Jouppi. "NVSim: A Circuit-Level Performance, Energy, and Area Model forEmerging Non-Volatile Memory" IEEE Transactions on Computer Aids Design (TCAD)., pp.994 - 1007, Vol.31 , No.7, July,2012.

  • [J8]. Yibo Chen, Yu Wang, Andres Takach, Yuan Xie. "Parametric Yield Driven Resource Binding in High-Level Synthesiswith Multi-Vth Vdd Library and Device Sizing" Journal of Electrical and Computer Engineering, vol.2012, Article ID105250, 14 pages, 2012.

  • [J9]. Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan. "A Syn-thesis Algorithm for Reconfigurable Single-Electron Transistor Arrays." ACM Journal of Emerging Technologies in ComputingSystems., Vol. 9, No. 1, Feb. 2013.

  • [J10]. Guangyu Sun, Huazhong Yang, and Yuan Xie."Performance/Thermal Aware Design of 3D Stacked L2 Caches forCMPs." ACM Transactions on Design Automation of Electronic Systems.,Vol. 17 No. 2, April 2012

  • [J11]. Yu Wang, Hong Luo, Ku He, Rong Luo, Huanzhong Yang, Yuan Xie. "Temperature-Aware NBTI Modeling and theImpact of Standby Leakage Reduction Techniques on Circuit Performance Degradation." IEEE Transactions on Dependableand Secure Computing (TDCS)., Vol.8, No.5, pp.756-769. Sept.-Oct., 2011.

  • [J12]. Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norm Jouppi. "Hybrid Checkpointing using Emerging Non-VolatileMemories for Future Exascale Systems." ACM Transactions on Architecture and Code Optimization (TACO), Vol.8, No. 2,Article 5, 29 pages, July 2011

  • [J13]. Vinay Saripalli, Guangyu Sun, Asit Mishra, Yuan Xie, Suman Datta, Vijaykrishnan Narayanan."Exploiting Het-erogeneity for Energy Efficiency in Chip Multiprocessors." IEEE Journal on Emerging and Selected Topics in Circuits andSystems (JETCAS),Vol.1, No.2, pp.109-119, June 2011

  • [J14]. Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen. "Stacking MRAM atop Microprocessors: An Architecture-Level Evaluation." IET Computers and Digital Techniques (IET CDT), Vo.5, No.3, pp.213-220, June 2011

  • [J15]. Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang. "Leakage Power and Circuit AgingOptimization by Gate Replacement Techniques." IEEE Transactions on Very Large Scale Integration Systems (TVLSI). Vol.19, No. 4, pp. 615-628, April. 2011.

  • [J16].Yuan Xie."Modeling, Architecture, and Applications for Emerging Non-volatile Memory Technologies." IEEEComputer Design and Test, Vol.28, No.1, pp.44-51, January 2011

  • [J17]. Xiaoxia Wu, Wei Zhao, Chandra Nimmagadda, Durodami Lisk, Mark Nakamoto, Sam Gu, Riko Radojcic, Matt Nowak, and Yuan Xie. "Electrical Characterization for Inter-tier Connections and Timing Analysis for 3D ICs." IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), pp.186-191, Vol. 20, No. 1, 2012.

  • [J18]. Shengqi Yang, Pallav Gupta, Marilyn Wolf, Dimitrios Serpanos, Yuan Xie, N. Vijaykrishnan. "Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling." ACM Transactions in Embedded Computing Systems (TECS), Vol. 11, No. 3, Sept. 2012.

  • [J19]. Feng Wang, Yibo Chen, Xiaoxia Wu, C. Nicopoulos, Yuan Xie, N. Vijaykrishnan. "Variation-aware Task Allocationand Scheduling for MPSoC." IEEE Transactions on CAD (TCAD), Vol 30, No.2, pp. 259-307, 2011

  • [J20]. Feng Wang and Yuan Xie."SER Analysis for Combinational Logic Using an Accurate Electrical Masking Model."IEEE Transactions on Dependable and Secure Computing (TDCS). Vol. 8, No. 1, 2011, pp.137-146.

  • [J21]. Xiaoxia Wu, Jian Li, Lixi Zhang, Evan Speight, Yuan Xie."Hybrid Cache Architecture with Disparate MemoryTechnologies." ACM Transactions on Architecture and Code Optimization (TACO). Vol. 7, No. 3, December 2010

  • [22]. Xiangyu Dong, Jishen Zhao, Yuan Xie. "Cost Analysis and Cost-driven Design for 3D ICs." IEEE Transactions on CAD(TCAD), Vol 29, No. 12, pp. 1959-1972, Dec. 2010.

  • [23]. Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, and Kaushik Roy. "Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance." IEEE Transactions on VLSI (TVLSI), Vol 18, No. 11, pp. 1621-1624,Nov. 2010.

  • [J24]. Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie."Test-access mechanism optimization for core-basedthree-dimensional SOCs." Microelectronics Journal, Volume 41 Issue 10, pp. 601-615, Oct. 2010

  • [J25]. Gabe Loh, Yuan Xie. "3D Stacked Microprocessor: Are We There Yet?" IEEE Micro, Volume 30 Issue 3, pp. 60-64,May. 2010

  • [J26]. Wei-lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut Kandemir, and Mary Jane Irwin. "Total Power Optimiza-tion for Combinational Logics Using Genetic Algorithms." Journal of VLSI Signal Processing. Vol. 58, No. 2, pp.145-160,Feb. 2010.

  • [J27]. Hong Luo, Yu Wang, Rong Luo, Huazhong Yang, Yuan Xie. "Temperature-aware NBTI Modeling Techniques in DigitalCircuits." IEICE Transactions on Electronics., No. 6, pp. 875-886, 2009

  • [J28]. Yuan Xie and Yibo Chen. "Statistical High Level Synthesis Considering Process Variations." IEEE Computer Designand Test, Special Issue on HLS, Vol. 26, Issue 4, pp.78-87, July-August, 2009

  • [J29]. Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie. "Scan-chain design and optimization for three-dimensional integrated circuits." ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol.5, Issue 2,pp.1-26, July, 2009

  • [J30]. M. DeBole, R. Krishnan, V. Balakrishnan, W. Wang, H. Luo, Y. Wang, Y. Xie, Y. Cao and N. Vijaykrishnan. "New-Age:A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components." International Journalof Parallel Programming., Vol. 37, No.4, pp.417-431, August, 2009.

  • [J31]. M. Mutyam, A. Mupid, F. Wang, N. Vijaykrishnan, Yuan Xie, M. Kandemir."Process Variation Aware AdaptiveCache Architecture and Management." IEEE Transactions on Computers., Vol. 58, No.7, pp.865-877, July, 2009.

  • [J32]. R. Rajaraman, V. Degalahal, J. S. Kim, N. Vijaykrishnan, Y. Xie, M. J. Irwin. "Modeling Soft Errors at Device andLogic Level for Combinational Circuits." IEEE Transactions on Dependable and Secure Computing (TDCS)., Vol. 6, No. 3,pp.202-216, June 2009.

  • [J33]. C. Celik, K.Unlu, K. Ramakrishnan, R. Rajaraman, N. Vijaykrishnan, M. J. Irwin, Y. Xie. "Thermal Neutron InducedSoft Error Rate Measurement in Semiconductor Memories and Circuits." Journal of Radioanalytical and Nuclear Chemistry.,Vol. 278, No.2, pp.509-512, Nov 2008.

  • [J34]. S. Srinivasan, R. Krishnan, P. Mangalagiri, Yuan Xie, and N. Vijaykrishnan."Towards Increasing FPGA Lifetime."IEEE Transactions on Dependable and Secure Computing (TDCS), Vol. 5, Issue 2, pp.115-127 Apr-Jun 2008.

  • [J35]. Shengqi Yang, W. Wang, W. Wolf, Yuan Xie, N. Vijaykrishnan."Case Study of Reliability-Aware and Low-PowerDesign." IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 16, Issue 7, pp.861-873, July 2008.

  • [J36]. Yuh-fang Tsai, Feng Wang, Yuan Xie, N. Vijaykrishnan, and M. J. Irwin."Design Space Exploration for Three-Dimensional Cache." IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.16, Issue 4, pp.444-455, Apr.2008 .

  • [J37]. Chang-hong Lin, Yuan Xie, and W.Wolf. "Code Compression for VLIW Embedded Systems Using a Self-Generating Table." IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 15. No. 10.,pp.1160-1171, Oct. 2007

  • [J38]. Feng Wang, Mike Debole, Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan, and M. J. Irwin. "On-chip Bus Thermal Analysis and Optimization." IET Computer and Digital Techniques, Vol. 1, No. 5., pp.590-599, 2007.

  • [J39]. Yuan Xie, W.Wolf, and H. Lekatsas. "Decompression Unit Design for VLIW Embedded Processors." IEEE Transactionson Very Large Scale Integration Systems (TVLSI), Vol. 15. No. 8, pp.975-980, Aug. 2007.

  • [J40]. Gabriel Loh, Yuan Xie, and Bryan Black. "Processor Design in Three-Dimensional Die-Stacking Technologies." IEEEMicro, Vol. 27. No. 3, pp.31-48, May/June 2007.

  • [J41]. Yuan Xie, Lin Li, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin."Reliability-Aware Co-synthesis for EmbeddedSystems." Journal of VLSI Signal Processing, Vol. 49, No.10, pp.87-99, March 2007.

  • [J42]. Yuan Xie, Wei-lun Hung. "Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design." Journal of VLSI Signal Processing, Vol. 45, No. 3, pp.177-189, December 2006.

  • [J43]. Yuan Xie, Gabriel Loh, Bryan Black, and Kerry Bernstein." Design Space Exploration for 3D Architecture." ACMJournal of Emerging Technologies for Computer Systems, Vol. 2. No. 2, pp.65-103, April 2006.

  • [J44]. N. Vijaykrishnan and Yuan Xie. " Reliability Concerns in Embedded System Designs." IEEE Computer, Vol. 39, No.1, pp.118-120, January 2006.

  • [J45]. Yuan Xie, W.Wolf, and H. Lekatsas. " Code Compression Using Variable-to-fixed Coding." IEEE Transactions on VeryLarge Scale Integration Systems (TVLSI), Vol. 14. No. 5, pp.525-536, January. 2006.

  • [J46]. Yuan Xie, Jiang Xu, W.Wolf. " Augmenting Platform-based Design with Synthesis Tools." Journal of Circuits, Systemsand Computers, Vol. 14. No. 5, pp.525-536, April. 2003.

Book

  • [1]. Yuan Xie "Emerging Memory Technologies: Design, Architecture, and Applications." Springer. 2013

  • [2]. Yuan Xie, Jason Cong, Sachin Sapatnekar. "Three-dimensional IC: Design, CAD, and Architecture." Springer. 2009

Book Chapters

  • [1]. Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan. "Thermal-aware 3D IC Designs." 3D Integration of Integrated Circuits. Editedby C. S. Tan, K. N. Chen and S. J. Koester, Pan Stanford Publishing Ltd. 2011

  • [2]. Yuan Xie, N. Vijaykrishnan, Chita Das. "3D Network-on-chip Architecture." Three-dimensional IC: Design, CAD, andArchitecture. Edited by Yuan Xie, Jason Cong, Sachin Sapatnekar. Springer. 2009.

  • [3]. Yuan Xie, Xiangyu Dong."System-level Cost Analsysis and Design Exploration for 3D ICs." Three-dimensional IC:Design, CAD, and Architecture. Edited by Yuan Xie, Jason Cong, Sachin Sapatnekar. Springer. 2009.

  • [4]. Degalahal, V., R. Ramanarayanan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin."Effect of Power Optimizations on SoftError Rate." IFIP Series on VLSI-SoC. pp. 1-20, 2006. Edited by R. Reis. Springer.

Refereed Conference Publications

  • [C1]. Tao Zhang, Cong Xu, Guangyu Sun, Yuan Xie. "CREAM: A Concurrent-Refresh-Aware DRAM Memory System." Toappear in Proceedings of The 20th IEEE International Symposium On High Performance Computer Architecture (HPCA) ,2014.

  • [C2]. Zhe Wang, Daniel Jimenez, Cong Xu, Guangyu Sun, Yuan Xie. "Adaptive Placement and Migration Policy for an STT-RAM-Based Hybrid Cache." To appear in Proceedings of The 20th IEEE International Symposium On High PerformanceComputer Architecture (HPCA) , 2014.

  • [C3]. Jia Zhan, Matt Poremba, Yi Xu, Yuan Xie "No:Leveraging Delta Compression for End-to-End Memory Access in NoCBased Multicores." Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC). 2014. (Best PaperNomination).

  • [C4]. Xing Hu, Yi Xu, Yu Hu, Yuan Xie "SwimmingLane: A Composite Approach to Mitigate Voltage Droop Effects in 3DPower Delivery Network." Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC). 2014.

  • [C5]. Qiaosha Zou, Dimin Niu, Yan Cao, Yuan Xie "3DLAT: TSV-Based 3D ICs Crosstalk Minimization Utilizing LessAdjacent Transition Code." Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC). 2014.

  • [C6]. Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie "Modeling and Design Analysis of 3D Vertical Resistive Memory - A LowCost Cross-Point Architecture." Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC). 2014.

  • [C7]. Jishen Zhao, Sheng Li, Doe Hyun Yoon, Norm Jouppi, Yuan Xie. "Kiln: Closing the Performance Gap Between SystemsWith and Without Persistence Support." Proceedings of IEEE/ACM International Conference on Microarchitecture (MICRO),2013. Best Paper Honorable Mention.

  • [C8]. Dimin Niu, Cong Xu, Naveen Muralimanoha, Norm Jouppi, Yuan Xie."Design of Cross-point Metal-oxide ReRAMEmphasizing Reliability and Cost." To appear in Proceedings of ACM/IEEE International Conference on Computer-AidedDesign (ICCAD), 2013.

  • [C9]. Dimin Niu, Qiaosha Zou, Cong Xu, Yuan Xie. "Low Power Multi-Level-Cell Resistive Memory Design with IncompleteData Mapping" To appear in Proceedings of ACM/IEEE International Conference on Computer Design (ICCD), 2013.

  • [C10]. Tao Zhang, Cong Xu, Guangyu Sun, Yuan Xie."Lazy Precharge: an Overhead-free Method to Reduce PrechargeOverhead for Memory Parallelism Improvement of DRAM System" To appear in Proceedings of ACM/IEEE InternationalConference on Computer Design (ICCD), 2013.

  • [C11]. Jia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijay Narayanan, Yuan Xie. "Designing Energy-Efficient NoCfor Real-Time Embedded Systems Through Slack Optimization." To appear in Proceedings of ACM/IEEE Design AutomationConference (DAC), 2013.

  • [C12]. Cong Xu, Dimin Niu, Naveen Muralimanohar, Yuan Xie,"Understanding the Trade-offs in Multi-Level Cell ReRAMMemory Design" To appear in Proceedings of ACM/IEEE Design Automation Conference (DAC), 2013.

  • [C13]. Jue Wang, Xiangyu Dong, and Yuan Xie "OAP: An Obstruction-Aware Cache Management Policy for STT-RAMLast-Level Caches" Proceedings of ACM/IEEE International Conference on Design Automation and Test in Europe (DATE),2013, Best Paper Candidate .

  • [C14]. Jue Wang, Xiangyu Dong, Norm Jouppi, and Yuan Xie "i2WAP: Improving Non-Volatile Cache Lifetime by Reduc-ing Inter- and Intra-Set Write Variations" Proceedings of IEEE International Symposium on High- Performance ComputerArhitecture Conference (HPCA), 2013, pp.234-245.,

  • [C15]. Yuanying Chang, Shieh-Chieh Huang, Matt Poremba, Vijaykrishnan Narayanan, Chung-Da King, and Yuan Xie " TS-Router: On Maximizing the Quality-of-Allocation in the On-Chip Network " Proceedings of IEEE International Symposiumon High- Performance Computer Arhitecture Conference (HPCA), 2013, pp.390-399.,

  • [C16]. Qiaosha Zou, Jing Xie, and Yuan Xie "Cost-driven 3D Design Optimization with Metal Layer Reduction Technique"Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), 2013.,

  • [C17]. Jing Xie, Yang Du, and Yuan Xie "CPDI: Cross-Power-Domain Interface Circuit Design in Monolithic 3D Technology"Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), 2013.,

  • [C18]. Wulong Liu, Haixiao Du, Yu Wang, Yuchuan Ma, Yuan Xie, Jinguo Quan, Huazhong Yang, "TSV-aware TopologyGeneration for 3D Clock Tree Synthesis". Proceedings of IEEE International Symposium on Quality Electronic Design(ISQED), 2013.,

  • [C19]. Jishen Zhao and Yuan Xie "Optimizing Bandwidth and Power of Graphics Memory with Hybrid Memory Technologiesand Adaptive Data Migration" Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD),2012, pp.xxx-xxx.,

  • [C20]. Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma and Huazhong Yang "Temporal Performance Degradation underRTN: Evaluation and Mitigation for Nanoscale Circuits" Proceedings of IEEE Computer Society Annual Symposium on VLSI(ISVLSI), 2012, pp.183-188,Best Paper Award.

  • [C21]. Matt Poremba and Yuan Xie"NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatileMemories" Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2012, pp.392-397.

  • [C22]. Jishen Zhao, Guangyu Sun, Gabriel Loh, Yuan Xie "Energy-efficient GPU Design with Reconfigurable In-packageGraphics Memory" Proceedings of ACM/IEEE International Symposium on Low Power Electronic Design (ISLPED), 2012,pp.403-408.,

  • [C23]. Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie "Design Trade-Offs for High Density Cross-Point Resistive Memory " Proceedings of ACM/IEEE International Symposium on Low Power Electronic Design (ISLPED),2012, pp.209-214.,

  • [C24]. Adwait Jog, Asit Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Chita Das, Ravi Iyer "Cache Revive: Archi-tecting Volatile STT-RAM Caches for Enhanced Performance " Proceedings of ACM/IEEE Design Automation Conference(DAC), 2012, pp.243-252.

  • [C25]. Jue Wang, Xiangyu Dong, Yuan Xie "Point and Discard: A Hard-Error-Tolerant Architecture for Non-Volatile Last Level Caches " Proceedings of ACM/IEEE Design Automation Conference (DAC), 2012, pp. 253-258.

  • [C26]. Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Yuan Xie "PS3-RAM: A Fast, Portable and Scalable StatisticalSTT-RAM Reliability Analysis Method " To appear in Proceedings of ACM/IEEE Design Automation Conference (DAC),2012, pp. 1187-1192.

  • [C27]. Yibo Chen, Guangyu Sun, Qiaosha Zou, Yuan Xie "3DHLS: Incorporating high-level synthesis in physical planning of3D ICs Proceedings of ACM/IEEE Design Automation and Test in Europe (DATE), 2012,

  • [C28]. Guangyu Sun, Cong Xu, Yuan Xie, Zhichao. Lv. "Modeling and Design Exploration of FBDRAM as On-chip Memory."Proceedings of ACM/IEEE Design Automation and Test in Europe (DATE), 2012,

  • [C29]. Jing Xie, Yu Wang, Yuan Xie "Yield-Aware Time-Efficient Testing and Self-fixing Design For TSV-Based 3D ICs ",(Invited Paper) Proceedings of ACM/IEEE Asia and South-Pacific Design Automation Conference, 2012,

  • [C30]. Dimin Niu, Yang Xiao, Yuan Xie "Low Power Memristor-Based ReRAM Design with Error Correcting Code", Pro-ceedings of ACM/IEEE Asia and South-Pacific Design Automation Conference, 2012, 99 accepted out of 288 submissions(34%)

  • [C31]. Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie "Thermal-aware Power NetworkDesign for IR Drop Reduction in 3D ICs", Proceedings of ACM/IEEE Asia and South-Pacific Design Automation Conference,2012, 99 accepted out of 288 submissions (34%)

  • [C32]. Qiaosha Zou, Yibo Chen, Alan Su, Yuan Xie "System-level Design Space Exploration for 3D SoCs", Proceedings ofACM/IEEE CODES+ISSS, 2011, (Invited Paper)

  • [C33]. Jishen Zhao, Cong Xu, Yuan Xie "Bandwidth-Aware Reconfigurable Cache Design with Hybrid Memory Technologies",Proceedings of ACM/IEEE Intl. Conf. on Computer-aided Design (ICCAD), 2011, pp. 48-55.

  • [C34]. Cong Xu, Dimin Niu, Xiaochun Zhu, Seung H. Kang, Matt Nowak and Yuan Xie "Device-Architecture Co-Optimizationof STT-RAM Based Memory for Low Power Embedded System", Proceedings of ACM/IEEE Intl. Conf. on Computer-aidedDesign (ICCAD), 2011, pp.463-470.

  • [C35]. Guangyu Sun, Eren Kursun, Jude Rivers, Yuan Xie "Improving the Vulnerability of CMPs to Soft Erros with 3DStacked Non-volatile Memory", Proceedings of ACM/IEEE Intl. Conf. on Computer Design (ICCD), 2011, pp. 366-372.

  • [C36]. Jue Wang, Xiangyu Dong, Guanyu Sun, Dimin Niu and Yuan Xie. "Energy-Efficient Multi-Level Cell Phase-ChangeMemory System with Data Encoding", To appear in Proceedings of ACM/IEEE Intl. Conf. on Computer Design (ICCD),2011, pp.175-182.

  • [C37]. Yibo Chen, Eren Kursun, Dave Motschman, Charles Johnson, Yuan Xie "Analysis and Mitigation of Lateral ThermalBlockage Effect of Through-Silicon-Via in 3D IC Designs", Proceedings of ACM/IEEE Intl. Symp. on Low Power ElectroncDevices (ISLPED), 2011, pp.397-402. Best Paper Award

  • [C38]. Chen, H.-W., S. Srinivasan, Y. Xie, N. Vijaykrishnan."Impact of Circuit Degradation on FPGA Design Security. ",Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2011 (ISVLSI 2011), pp.230-235.

  • [C39]. Jin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, Zhiwen Liu "F2BFLY: An On-Chip Free-Space Optical Networkwith Wavelength-Switching", Proceedings of ACM/IEEE 25th International Conference on Supercomputing (ICS), 2011, pp.348-358. (35 accepted out of 161 submissions, 21%)

  • [C40]. A. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, N. Vijaykrishnan, C. Das "Architecting NoCs for Stacked 3DSTT-RAM Caches in CMPs", Proceedings of ACM/IEEE International Conference on Computer Architecture (ISCA), 2011,pp.69-80, (40 accepted out of 208 submissions, 19%)

  • [C41]. Guangyu Sun, C. Hughes, C. Kim, Jishen Zhao, C. Xu, Yuan Xie, Yen-KuanChen "Moguls: a Model to Explore Mem-ory Hierarchy for Throughput Computing", Proceedings of ACM/IEEE International Conference on Computer Architecture(ISCA), 2011, pp.377-388. (40 accepted out of 208 submissions, 19%)

  • [C42]. Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Vijaykrishnan Narayanan, Yuan Xie, Suman Dutta"Au-tomated Mapping for Reconfigurable Single Electron Transistor Arrays", Proceedings of ACM/IEEE Design AutomationConference (DAC), 2011, pp.878-883.

  • [C43]. Vijaykrishnan, N., V. Saripalli, R. Mukundrajan, G. Sun*, K. Swaminathan, Y. Xie, S. Datta "Enabling ArchitecturalInnovations using Non-Volatile Memory.", In Proceedings of Twenty-First ACM Great Lakes Symposium on VLSI (GLSVLSI2011), pp.439-444, 2011

  • [C44]. Cong Xu, Xiangyu Dong, Norm Jouppi, and Yuan Xie "Design Implications of Memristor-Based RRAM Cross-PointStructures", In Proceedings of ACM/IEEE Design Automation and Test in Europe Conference (DATE), pp.734-739, 2011

  • [C45]. Jishen Zhao, Xiangyu Dong, and Yuan Xie "An Energy-Efficient 3D CMP Design with Fine-Grained Voltage Scaling",In Proceedings of ACM/IEEE Design Automation and Test in Europe Conference (DATE), pp.539-542, 2011

  • [C46]. Shekhar SriKantaiah, Emre Kultursay, Tao Zhang, Mahmut Kandemir, Mary Jane Irwin, and Yuan Xie, "MorphCache:A Reconfigurable Adaptive Multi-level Cache Hierarchy for CMPs", Proceedings of IEEE International Symposium on High-Performance Computer Arhitecture Conference (HPCA), pp. 231-242, 2011

  • [C47]. Jin Ouyang and Yuan Xie "Enabling Quality-of-Service in Nanophotonic Network-on-Chip", Proceedings of ACM/IEEEAsia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011, pp.351-356.

  • [C48]. Xiangyu Dong and Yuan Xie "AdaMS: Adaptive MLC/SLC Phase-Change Memory Design for File Storage", Proceed-ings of ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.31-36, 2011

  • [C49]. Wulong Liu, Yu Wang, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang"On-Chip Hybrid Power Supply Systemfor Wireless Sensor Nodes", Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC),pp.43-48, 2011

  • [C50]. Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie "A Frequent-Value Based PRAM Memory Architecture", Proceedingsof ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.211-216, 2011

  • [C51]. Jin Ouyang and Yuan Xie "LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support",Proceedings of Intl. Symp. on Microarchitecture (MICRO 2010), pp.351-356, 2010

  • [C52]. Tao Zhang, Kui Wang, Yi Feng, Yan Chen, Qun Li, Bing Shao, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng,Yong-long Lin, "A 3D SoC Design for H.264 Application With On-Chip DRAM Stacking", Proceedings of IEEE International3D System Integration Conference (3DIC), 2010

  • [C53]. Jing Xie, Xiangyu Dong, Yuan Xie "3D Memory Stacking for Fast Checkpointing/Restore Applications", Proceedingsof IEEE International 3D System Integration Conference (3DIC), 2010

  • [C54]. Tao Zhang, Kui Wang, Yi Feng, Lian Duan, Xiaodi Song, Yuan Xie, Xu Cheng, Yong-long Lin, "A Customized Designof DRAM Controller for On-Chip 3D DRAM Stacking", Proceedings of Custom IC Conference (CICC 2010), 2010

  • [C55]. Xiangyu Dong, Yuan Xie, Norm Jouppi, Naveen Muralimanohar "Simple but Effective Heterogeneous Main Memorywith On-Chip Memory Controller Support" Proceedings of Supercomputing (SC 2010), 2010.

  • [C56]. Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie, Qiang Xu "Modeling TSV Open Defects in 3D-Stacked DRAM", Proceedingsof Int. Conf. on Testing (ITC 2010), Nov, 2010.

  • [C57]. Matt Poremba, Yuan Xie, Marilyn Wolf."Accelerating Adaptive Background Subtraction with GPU and CBEAArchitecture", Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), pp.305-310, Oct. 2010.

  • [C58]. Jin Ouyang, Jing Xie, Matt Poremba, Yuan Xie " Design Methodology of 3D Network-on-Chip with Inductive/Capacitive-Coupling Vertical Interconnect" Proceedings of Int. Conf. on CAD (ICCAD), Nov, 2010. pp.477-482.

  • [C59]. Yibo Chen, Dimin Niu, Yuan Xie, Krish Chakrabarty "Cost-Effective Integration of Three-Dimensional (3D) ICsEmphasizing Testing Cost Analysis" Proceedings of Int. Conf. on CAD (ICCAD), Nov, 2010. pp. 471-476

  • [C60]. Yibo Chen, Jishen Zhao, Yuan Xie "3D-NonFAR: Three-Dimensional Non-Volatile FPGA ARchitecture Using PhaseChange Memory." Proceedings of Intl. Symp. Low Power Electronic Devices (ISLPED). August, 2010. pp.55-60.(25%acceptance rate).

  • [C61]. Dimin Niu, Yiran Chen, Yuan Xie "Dual-element Memristor-Based Memory Design." Proceedings of Intl. Symp. LowPower Electronic Devices (ISLPED). August, 2010. pp. 25-30. (25% acceptance rate).

  • [C62]. Jishen Zhao, Xiangyu Dong, Yuan Xie "Cost-Aware Three-Dimensional (3D) Many-Core Multiprocessor Design."Proceedings of Design Automation Conference (DAC). 2010. pp.126-131. (24% acceptance rate).

  • [C63]. Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie "Impact of Process Variations on Emerging Memristor." Proceedings ofDesign Automation Conference (DAC). 2010. pp. 877-882. (24% acceptance rate).

  • [C64]. Xiaoxia Wu, Guangyu Sun, Reetuparna Das, Yuan Xie, Jian Li, Chita R. Das "Cost-driven 3D Integration withInterconnect Layers." Proceedings of Design Automation Conference (DAC). 2010. pp.150-155. (24% acceptance rate).

  • [C65]. Yongsoo Joo, Dimin Niu, Guangyu Sun, Xiangyu Dong, Yuan Xie "Energy- and Endurance-Aware Design of PhaseChange Memory Caches." Proceedings of Design Automation and Test in Europe (DATE). 2010. pp.136-141. (25% acceptancerate).

  • [C66]. Guangyu Sun, Yongsoo Joo, Yibo Chen, Yuan Xie, Yiran Chen, Helen Li "A Hybrid Solid-State Storage Architecturefor Performance, Energy Consumption and Lifetime Improvement." Proceedings of High Performance Computer Architecture(HPCA). 2010. (18% acceptance rate).

  • [C67]. Yuan Xie "Processor Architecture Design Using 3D Integration Technology.(Invited Paper)" Proceedings of VLSIDesign. 2010.

  • [C68]. Yibo Chen, Yu Wang, Yuan Xie, Andres Takach "Parametric Yield Driven Resource Binding in Behavioral Synthesiswith Multi-Vth/Vdd Library." Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC). 2010.pp.781-786. (33% acceptance rate(115/340)) (Best Paper Nomination).

  • [C69]. Yibo Chen, Yu Wang, Yuan Xie, Andres Takach "Minimizing Leakage Power in Aging-Bounded High-level Synthesiswith Design Time Multi-Vth Assignment." Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC).2010. pp.689-694. (33% acceptance rate(115/340)).

  • [C70]. Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie "Energy and Performance Driven Circuit Design for Emerging Phase-Change Memory." Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC). 2010. (33% acceptancerate(115/340)).

  • [C71]. Paul Falkstern, Yao-wen Chang, Yuan Xie, Yu Wang "Three Dimensional Integrated Circuit (3D IC) Floorplan andPower/Ground Network Co-synthesis." Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC).2010. (33% acceptance rate(115/340)).

  • [C72]. Xiangyu Dong, Naveen Muralimanohar, Norm Jouppi, Richard Kaufmann, Yuan Xie "Leveraging 3D PCRAM Tech-nologies to Reduce Checkpoint Overhead for Future Exascale Systems." Proceedings of International Conference on HighPerformance Computing, Networking, Storage and Analysis (SC). 2009. (22% acceptance rate(59/261)).

  • [C73]. Xiangyu Dong, Norm Jouppi, Yuan Xie "PCRAMsim: System-Level Performance, Energy, and Area Modeling forPhase-Change RAM." Proceedings of International Conference on Computer-Aided Design (ICCAD). 2009. pp 269-275.(26% acceptance rate(115/438)).

  • [C74]. Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie "Intrinsic NBTI-Variability Aware Statistical Pipeline PerformanceAssessment and Tuning." Proceedings of International Conference on Computer-Aided Design (ICCAD). 2009. pp 164-171.(26% acceptance rate(115/438)).

  • [C75]. Xiaoxia Wu, Jian Li, Lixi Zhang, Evan Speight, Yuan Xie."Hybrid Cache Architecture with Disparate MemoryTechnologies." Proceedings of International Symposium on Computer Architecture (ISCA), pp.34-45, June. 2009.

  • [C76]. Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang. "Gate Replacement Techniques forSimultaneous Leakage and Aging Optimization." Proceedings of Design Automation and Test in Europe (DATE), pp. 324-333.April. 2009.

  • [C77]. Balaji Vaidyanathan, Anthony Oates, Yuan Xie, Yu Wang."NBTI-Aware Statistical Circuit Delay Assessment."Proceedings of Intl. Symp. on Quality Electronics Device (ISQED), March. 2009.

  • [C78]. Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang. "On the efficacyof Input Vector Control to mitigate NBTI effects and leakage power." Proceedings of Intl. Symp. on Quality Electronics Device(ISQED), March. 2009.

  • [C79]. Luca P. Carloni, Partha Pande, and Yuan Xie . "Networks-on-chip in emerging interconnect paradigms: Advantagesand challenges." Proceedings of 3rd ACM/IEEE Intl. Symp. on Networks-on-chip, pp. 93-102. May. 2009.

  • [C80]. Xiaoxia Wu, Jian Li, Lixi Zhang, Evan Speight, Yuan Xie. "Power and Performance of Read-write aware hybrid cacheswith non-volatile memories." Proceedings of Design Automation and Test in Europe (DATE), pp. 737-742. April. 2009.

  • [C81]. Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen."A Novel MRAM Stacking Architecture for Chip-multiprocessors (CMP)." Proceedings of High Performance Computer Architecture (HPCA), pp. 239-249. Feb. 2009. (19%acceptance rate(34/185)).

  • [C82]. Xiangyu Dong and Yuan Xie. "System-level Cost Analysis and Design Exploration for 3D ICs." Proceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), Jan. 2009. Best Paper Award Nomination. (32% acceptancerate(116/355)).

  • [C83]. Mike Debole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan "A Criticality-Driven Microarchitectural ThreeDimensional (3D) Floorplanner." Proceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), Jan. 2009. (32% acceptance rate(116/355)).

  • [C84]. Feng Wang, Andres Takach, and Yuan Xie. "Variation-Aware Resource Sharing and Binding in Behavioral Synthesis."Proceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), Jan. 2009. (32% acceptance rate(116/355)).

  • [C85]. Yibo Chen and Yuan Xie. "Tolerating Process Variations in High-Level Synthesis Using Transparent Latches." Pro-ceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), Jan. 2009. (32% acceptance rate(116/355)).

  • [C86]. Mike Debole, Wenping Wang, Yu Wang, Yuan Xie, Vijay Nayaranan, Yu Cao. "A Framework for Estimating NBTIDegradation of Microarchitectural Components" Proceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), Jan. 2009. (32% acceptance rate(116/355)).

  • [C87]. P. Mangalagiri, S. Bae, R. Krishnan, Yuan Xie, N. Vijaykrishnan. "Thermal-Aware Reliability Analysis for PlatformFPGAs " Proceedings of International Conference on Computer Aided Design (ICCAD), pp. 722-727, Nov. 2008. (122 out of458 submissions, 27% acceptance rate).

  • [C88]. Xiaoxia Wu, Yibo Chen, Krish Chakrabarty, and Yuan Xie. " Test-Access Mechanism Optimization for Core-BasedThree-Dimensional SOCs." Proceedings of International Conference on Computer Design (ICCD), pp.212-218 Oct. 2008.

  • [C89]. Yibo Chen, Feng Wang, Yuan Xie "ILP-based Scheme for Timing Variation-aware Scheduling and Resource Binding"Proceedings of System-on-Chip Conference, pp.27-30, Sept. 2008.

  • [C90]. Jin Ouyang, Yuan Xie "Power Optimization for FinFET-based Circuits Using Genetic Algorithms" Proceedings ofSystem-on-Chip Conference, pp. 211-214, Sept. 2008.

  • [C91]. Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, N. Vijaykrishnan, Chita R. Das"MIRA: A Multi-Layered On-Chip Interconnect Router Architecture" Proceedings of International Symopsium on ComputerArchitecture (ISCA), June. 2008. (37 out of 259 submissions, 14% acceptance rate)

  • [C92]. Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Helen Li, Yiran Chen "Circuit and Microarchitecture Evaluationof 3D Stacking Magnetic RAM (MRAM) as a Universal Memory" Proceedings of Design Automation Conference (DAC),pp.554-559, June. 2008. (138 out of 639 submissions, 21% acceptance rate)

  • [C93]. Hai Lin, Guangyu Sun, Yunsi Fei, Yuan Xie, Anand Sivasubramaniam "Thermal-aware Design Considerations forApplication-Specific Instruction Set Processor" in Proceedings of International Symposium on Appication Specific Processors,June. 2008. (19 out of 64 submissions, 29% acceptance rate)

  • [C94]. Xiangyu Dong, Xiaoxia Wu, Yuan Xie "Cost Analysis and Cost-driven EDA flow for 3D ICs" in Proceedings of 3D-SICConference, May. 2008.

  • [C95]. Feng Wang, Guangyu Sun, Yuan Xie. "A Variation Aware High Level Synthesis Framework." Proceedings of DesignAutomation and Test in Europe (DATE),pp.1063-1068, Mar. 2008. (198 out of 839 submissions, 23% acceptance rate)

  • [C96]. Feng Wang, Xiaoxia Wu, Yuan Xie. "Variability-Driven Module Selection with Joint Design Time Optimization andPost-Silicon Tuning." To appear in Proceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), Jan. 2008.Best Paper Award. (29% acceptance rate for regular papers (100/351)).

  • [C97]. Feng Wang, Xiaoxia Wu, C. Nicopoulos, Yuan Xie, N. Vijaykrishnan. "Variation-aware Task Allocation and Schedulingfor MPSoC." Proceedings of International Conference on Computer Aided Design (ICCAD), pp. 138-149, Nov. 2007. (139out of 510 submissions, 27% acceptance rate).

  • [C98]. Xiaoxia Wu, Paul Falkenstern, and Yuan Xie."Scan Chain Design for Three-dimentional(3D) ICs." Proceedings ofInternational Conference on Computer Design (ICCD), pp.208-214, Oct. 2007. (88 out of 259 submissions, 33% acceptancerate).

  • [C99]. S. Srinivasan, P. Mangalagiri, Yuan Xie, N. Vijaykrishnan. "FPGA Routing Architecture Analysis Under Variations."Proceedings of International Conference on Computer Design (ICCD), pp.152-157, Oct.2007.(88 out of 259 submissions,33% acceptance rate).

  • [C100]. H. Luo, Y. Wang, K. He, R. Luo, H. Yang, and Yuan Xie."A Novel Gate-level NBTI Delay Degradation Modelwith Stacking Effect." To appear in Proceedings of International Workshop on Power And Timing Modeling, Optimizationand Simulation (PATMOS), Sept. 2007.

  • [C101]. J. Kim, C. Nicopoulos, D. Park, R. Das, Yuan Xie, N. Vijaykrishnan, C. Das. "A Novel Dimensionally-DecomposedRouter for On-Chip Communication in 3D Architectures." Proceedings of the Annual International Symposium on ComputerArchitecture (ISCA), pp. 138-149, June 2007. (46 papers accepted out of 204 submissions. 23% acceptance rate)

  • [C102]. Alex K. Jones, Steven Levitan, Rob A. Rutenbar, and Yuan Xie. "Collaborative VLSI-CAD Instruction in the Digital Sandbox." Proceedings of IEEE International Conference on Microelectronic Systems Education, pp. 141-142, June 2007.

  • [C103]. Feng Wang, Yuan Xie, and Hai Ju."A Novel Criticality Computation Method in Statistical Timing Analysis."Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 1611-1616, April 2007.(208 papers accepted out of 933 submissions. 22% acceptance rate)

  • [C104]. Y. Wang, H. Luo, K. He, R. Luo, Yuan Xie, and H. Yang."Temperature-aware NBTI Modeling and the Impactof Input Vector Control on Performance Degradation." Proceedings of IEEE International Conference on Design Automationand Test in Europe (DATE), pp. 546-551, April 2007. (208 papers accepted out of 933 submissions. 22% acceptance rate)

  • [C105]. R. Krishnan, R. Ramanarayanan, S. Srinivasan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin."Variation Impact onSER of Combinatorial Circuits." Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp.911-916, March 2007. (93 papers accepted out of 292 submissions. 31% acceptance rate)

  • [C106]. A. Mupid, M. Mutyam, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. "Variation Analysis of CAM Cells." Proceedings ofIEEE International Symposium on Quality Electronic Design (ISQED), pp. 333-338, March 2007. (93 papers accepted out of292 submissions. 31% acceptance rate)

  • [C107]. H. Luo, Y. Wang, K. He, R. Luo, H. Yang, Yuan Xie. "Modeling of PMOS NBTI Effect Considering TemperatureVariation." Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 139-144, March 2007.(93 papers accepted out of 292 submissions. 31% acceptance rate)

  • [C108]. Feng Wang and Yuan Xie. "Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical MaskingModel." Proceedings of IEEE International Conference on VLSI Design (VLSID), pp.165-170, Jan.2007.(141 papersaccepted out of 432 submissions. 32% acceptance rate)

  • [C109]. Balaji Vaidyanathan, W-L. Hung, Feng Wang, Yuan Xie, N. Vijaykrishnan, M. J. Irwin. "Architecting MicroprocessorComponents in 3D Design Space." Proceedings of IEEE International Conference on VLSI Design (VLSID), pp. 103-108, Jan.2007. (141 papers accepted out of 432 submissions. 32% acceptance rate)

  • [C110]. Balaji Vaidyanathan, Yuan Xie, N. Vijaykrishnan, R. Luo."Leakage Optimized DECAP Design for FPGAs."Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 560-563, Dec. 2006.

  • [C111]. Wei-lun Hung, Xiaoxia Wu, Yuan Xie."Guaranteeing Performance Yield in High-Level Synthesis." Proceedings ofInternational Conference on Computer Aided Design (ICCAD), pp.303-309, Nov. 2006. Best paper award nomination.(130papers accepted out of 537 submissions. 24% acceptance rate).

  • [C112]. Qian Ding, R. Luo, H. Wang, H. Yang and Yuan Xie. "Modeling the Impact of Process Variation on Critical ChargeDistribution." Proceedings of IEEE International System-on-Chip Conference (SOCC), pp. 243-237, Sept. 2006. (58 regularpapers accepted out of 177 submissions. 31% acceptance rate)

  • [C113]. Balaji Vaidyanathan and Yuan Xie. "Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through CodeCompression." Proceedings of IEEE International System-on-Chip Conference (SOCC), pp.93-97, Sept.2006.(58 papersaccepted out of 177 submissions. 31% acceptance rate)

  • [C114]. Xiaoxia Wu, Feng Wang, and Yuan Xie."Analysis of Subthreshold Finfet Circuit for Ultra-low Power Design."Proceedings of IEEE International System-on-Chip Conference (SOCC), pp. 91-93, Sept. 2006.

  • [C115]. S. Srinivasan, M. Prasanth, S. Karthink, Yuan Xie, N. Vijaykrishnan. "FLAW: FPGA Lifetime Awareness." Proceed-ings of the 43rd Design Automation Conference (DAC), pp. 630-635, July. 2006. (209 papers accepted out of 865 submissions.24% acceptance rate)

  • [C116]. F. Li,C. Nicopoulos, T. Richardson, Yuan Xie, N. Vijaykrishnan, M. Kandemir. "Design and Management of 3D ChipMultiprocessors using Network-in-memory." Proceedings of the Annual International Symposium on Computer Architecture (ISCA), pp. 130-141, June. 2006. (31 papers accepted out of 234 submissions. 13% acceptance rate)

  • [C117]. Feng Wang, Yuan Xie. "An Accurate and Efficient Model of Electrical Masking Effect for Soft Errors in Combinatorial Logic." Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE), April 2006.

  • [C118]. B. Vaidyanathan, Yuan Xie, N. Vijaykrishnan. "Soft Error Analysis and Optimizations of C-elements in Asynchronous Circuits." Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE), April 2006.

  • [C119]. R. Ramanarayanan, R. Krishnan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. "Temperature and Voltage Scaling Effects on Electrical Masking." Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE), April 2006.

  • [C120]. Wei-lun Hung, G. Link, Yuan Xie, N. Vijaykrishnan, M. J. Irwin. "Interconnect and Thermal-aware Floorplanning for 3D Microprocessors." Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 98-104, March. 2006. (93 papers accepted out of 256 submissions. 36% acceptance rate)

  • [C121]. Feng Wang, Yuan Xie, N. Vijaykrishnan and M. J. Irwin."On-chip Bus Thermal Analysis and Optimization."Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 850-855, March 2006.(233 papers accepted out of 834 submissions. 28% acceptance rate)

  • [C122]. Feng Wang, Yuan Xie, K. Bernstein and Y. Luo. "Dependability Analysis of Nano-scale FinFET Circuits." Proceedingsof the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI), pp. 399-404, March 2006.

  • [C123]. M. Mutyam, M. Eze, N. Vijaykrishnan, Yuan Xie."Delay and Energy Efficient Data Transmission for On-ChipBuses." Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI), pp. 355-360, March 2006.

  • [C124]. S. Yang, W. Wolf, N. Vijaykrishnan, Yuan Xie. "Reliability-Aware SOC Voltage Islands Partition and Floorplan."Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI), pp. 343-348, March 2006.

  • [C125]. O. Ozturk, F. Wang, M. Kandemir, Yuan Xie."Optimal Topology Exploration for Application-Specific 3D Archi-tectures." Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 390-395, Jan. 2006. (135papers accepted out of 432 submissions. 31% acceptance rate)

  • [C126]. Ramanarayanan, R., J. S. Kim, N. Vijaykrishnan, Yuan Xie, M. J. Irwin."SEAT-LA: A Soft Error Analysis toolfor Combinational Logic." Proceedings of IEEE International Conference on VLSI Design, pp. 499-502, Jan. 2006. (26.8%acceptance rate for regular papers (88 out of 328 submissions))

  • [C127]. T. Richardson, C. Nicopoulos, D. Park, N. Vijaykrishnan, Yuan Xie, C. R. Das. "A Hybrid SoC Interconnect withDynamic TDMA-Based Transaction-Less Buses and On-Chip Networks." Proceedings of IEEE International Conference onVLSI Design, pp. 499-502, Jan. 2006. (26.8% acceptance rate for regular papers)

  • [C128]. R. Luo, H. Luo, H. Yang, Yuan Xie. "An Instruction Level Analytical Power Model for Designing Low Power SOC."Proceedings of IEEE International Conference on ASICs, pp.1070-1073, Oct. 2005.

  • [C129]. T. Richardson and Yuan Xie. "Evaluation of Thermal-Aware Design Techniques for Microprocessors." Proceedings ofIEEE International Conference on ASICs, pp.62-65, Oct. 2005.

  • [C130]. W-L. Hung, G. Link, Yuan Xie, N. Vijaykrishnan, N. Dhanwada, J. Conner. "Temperature-Aware Voltage IslandsArchitecting in System-on-Chip Design." Proceedings of IEEE International Conference on Computer Design (ICCD), pp.689-696, Oct. 2005. (101 out of 313 submissions, 32% acceptance rate)

  • [C131]. S. K. Narayanan, G. Chen, M. Kandemir, Yuan Xie. "Temperature-Sensitive Loop Parallelization for Chip Multi-processors." Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 677-682, Oct. 2005. (101 outof 313 submissions, 32% acceptance rate)

  • [C132]. Y-F. Tsai, Yuan Xie, N. Vijaykrishnan, M. J. Irwin. "Three-Dimensional Cache Design Exploration Using 3DCacti."Proceedings of IEEE International Conference on Computer Design (ICCD), pp.519-524, Oct.2005.(101 out of 313submissions, 32% acceptance rate)

  • [C133]. D. Hostetler and Yuan Xie. " Adaptive Power Management in Software Radios Using Resolution Adaptive Analogto Digital Converters." Proceedings of IEEE International Symposium on VLSI (ISVLSI), pp. 186-191, May. 2005.

  • [C134]. W-L. Hung, Yuan Xie, N. Vijaykrishnan, C. Addo-Quaye, T. Theocharides, M. J. Irwin "Thermal-Aware Floorplan-ning Using Genetic Algorithms." Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 634-639,Mar. 2005. (83 out of 222 submissions, 37% acceptance rate)

  • [C135]. S. Tosun, O. Ozturk, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie."An ILP Formulation for Reliability-OrientedHigh-Level Synthesis." Proceedings of International Symposium on Quality Electronic Design (ISQED), pp.364-369, Mar.2005. (83 out of 222 submissions, 37% acceptance rate)

  • [C136]. S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie."Reliability-Centric Hardware/Software Co-design."Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 364-369, Mar. 2005. (83 out of 222 submissions, 37% acceptance rate)

  • [C137]. S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie. "Reliability-centric High-level Synthesis." Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 1258-1263, March 2005. ( 176 papers accepted out of 825 submissions. 21% acceptance rate)

  • [C138]. S. Yang, W. Wolf, N. Vijaykrishnan, Yuan Xie. "Power Attack Resistant Crypto Design: A Dynamic Voltage and Frequency Switching Approach." Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 64-69, March 2005. ( 21% acceptance rate)

  • [C139]. Wei-lun Hung, Yuan Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. "Thermal-Aware Allocation and Scheduling for Systems-on-a-Chip Design." Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 898-899, March 2005. ( 21% acceptance rate)

  • [C140]. Y-F Tsai, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. "Leakage-Aware Interconnect for On-Chip Network." Proceedingsof IEEE International Conference on Design Automation and Test in Europe (DATE), pp.230-231, March 2005.( 21%acceptance rate)

  • [C141]. J.Conner,Yuan Xie, M. Kandemir, R. Dick, G. Link."FD-HGAC: A Hybrid Heuristic/Genetic Algorithm Hard-ware/Software Co-synthesis Framework with Fault Detection." Proceedings of the Asia South Pacific Design AutomationConference (ASP-DAC)., pp. 709-712, Jan. 2005. (99 regular papers accepted out of 692 submissions (14.3%))

  • [C142]. S. Yang, W. Wolf, W. Wang, N. Vijaykrishnan, Yuan Xie. "Low-Leakage Robust SRAM Cell Design for Sub-100nmTechnologies." Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC)., pp. 539-544, Jan. 2005.14.3% acceptance rate for regular papers (99 regular papers accepted out of 692 submissions (14.3%))

  • [C143]. Y-F. Tsai, N. Vijaykrishnan, M. J. Irwin, Yuan Xie. "Influence of Leakage Reduction Techniques on Delay/LeakageUncertainty." Proceedings of the 18th International Conference on VLSI Design (VLSID), pp. 374-379, Jan. 2005. (97 regularpapers accepted out of 352 submissions (28%)).

  • [C144]. S. Yang, W. Wolf, W. Wang, N. Vijaykrishnan, Yuan Xie."Accurate Stacking Effect Macro-Modeling of LeakagePower in Sub-100nm Circuits." Proceedings of the 18th International Conference on VLSI Design (VLSID), pp. 165-170, Jan.2005. (97 regular papers accepted out of 352 submissions (28%)).

  • [C145]. S. Srinivasan, A. Gayasen, N. Vijaykrishnan, M. Kandemir, Yuan Xie, M. J. Irwin." Improving Soft-error Toleranceof FPGA Configuration Bits." Proceedings of International Conference on Computer Aided Design (ICCAD), Nov.2004.(24% acceptance rate).

  • [C146].W-L Hung, C. Addo-Quaye, T. Theocharides, Yuan Xie, N. Vijaykrishnan, M. J. Irwin."Thermal-Aware IPVirtualization and Placement for Networks-on-Chip Architecture." Proceedings of IEEE International Conference on ComputerDesign (ICCD), pp. 430-437, Oct. 2004. (84 out of 226 submissions, 37% acceptance rate.)

  • [C147]. Yuan Xie, L. Li, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. "Reliability-aware Cosynthesis for Embedded Systems."Proceedings of IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP), pp. 41-50, Sept. 2004.

  • [C148]. W-L. Hung,Yuan Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin."Total Power Optimization Through Simul-taneously Multiple-VDD Multiple-VTH Assignment and Device Sizing With Stack Forcing." Proceedings of InternationalSymposium on Low Power Electronics and Design (ISLPED 2004), pp. 144-149, Aug. 2004. 34% acceptance rate)

  • [C149]. W. Xu, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. "Design of a Nanosensor Array Architecture." Proceedings of GreatLakes Symposium on VLSI(GLSVLSI), pp. 298-303, Apr. 2004. (23 full papers accepted out of 235 submissions, 10% rate)

  • [C150]. V. Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. "The Effect of Threshold Voltages on theSoft Error Rate." Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 503-508, Mar. 2004.(49 papers accepted out of 148 submissions, 33%)

  • [C151]. C-H. Lin, W. Wolf, and Yuan Xie."LZW-based Code Compression for VLIW Embedded Systems." Proceedingsof IEEE International Conference on Design Automation and Test in Europe (DATE), pp.76-81, Feb.2004.(181 papersaccepted out of 780 submissions (23%))

  • [C152]. Yuan Xie."Analysis of Two Code Compression Algorithms for Embedded Systems." Proceedings of International Conference on ASIC (ASICON), pp. 773-776. Oct. 2003.

  • [C153]. Yuan Xie, Wayne Wolf, H. Lekatsas. "Code Compression Using Arithmetic Coding Based Variable-to-fixed Coding." Proceedings of Data Compression Conference(DCC 2003), pp. 382-391, Mar. 2003.

  • [C154]. Yuan Xie, W. Wolf, and H. Lektasas. "Profile-driven Code Compression." Proceedings of IEEE International Confer- ence on Design Automation and Test in Europe (DATE), pp. 76-81, Mar. 2003. (152 out of 590 submissions (25%))

  • [C155]. Yuan Xie, W. Wolf, and H. Lektasas. "Code Compression for VLIW Using Variable-to-fixed Coding." Proceedings of Fifteenth International Symposium on System Synthesis (ISSS 2002), pp. 138-143, Oct. 2002. (24 out of 71 submissions (33%))

  • [C156]. Yuan Xie, W. Wolf, and H. Lektasas. "A Code Decompression Architecture for VLIW Processors." Proceedings of the Thirty-Fourth International Symposium on Microarchitecture (MICRO-34). pp. 66-75. (29 out of 144 submissions, 20% acceptance rate)

  • [C157]. Yuan Xie, W. Wolf, and H. Lektasas. "Compression Ratio and Decompression Overhead Tradeoffs in Code Com- pression for VLIW Architectures." Proceedings of the Fourth International Conference on ASIC (ASICON). Best Paper Award.

  • [C158]. Yuan Xie, W. Wolf. "ASICosyn: Co-Synthesis of Coditional Task Graphs with Custom ASICs." Proceedings of theFourth International Conference on ASIC (ASICON).

  • [C159]. Yuan Xie, W. Wolf. "Allocation and Scheduling of Conditional Task Graphs in Co-synthesis." Proceedings of IEEEInternational Conference on Design Automation and Test in Europe (DATE), pp. 620-625, Mar. 2001. (81 full papers out of300 submissions (27%))

  • [C160]. Yuan Xie, Hua Lin, Zhao Wu, W. Wolf. "CAD Techniques for Multimedia System Design." Proceedings of Synthesisand System Integration of MIxed Technologies (SASIMI), Mar. 2000.

  • [C161]. Yuan Xie and Wayne Wolf."Co-synthesis with Custom ASICs." Proceedings of the Asia South Pacific DesignAutomation Conference (ASP-DAC), pp. 129-134, Jan. 2000.