A three dimensional (3D) chip is a stack of multiple device layers with direct vertical interconnects tunneling through them. A key benefit of this approach over a traditional two dimensional chip is the ability to reduce the length of long interconnects. Prior efforts have focused on developing different fabrication techniques involved in stacking multiple device layers and in forming the vertical interconnects. The size and density of the vertical interconnects that can tunnel between the different device layers varies based on the underlying technology used to fabricate the 3D chips.  To efficiently exploit the benefits of 3D technologies, design techniques and methodologies for supporting 3D designs are imperative.

Our 3D IC research projects were supported by NSF, SRC, DOE, DARPA, IBM, Qualcomm, and ITRI, with 3D chip fabrication supported by MITLL, Tezzaron, and IMEC.

New: The book "Three-dimensional IC: Design, CAD, and Architecture" edited by Yuan Xie, Jason Cong, Sachin Sapatnekar is published by Springer.

Tool Release:

• 3DCACTI --- 3DCACTI is a tool for estimating the optimum access times, and power dissipation of a cache using 3D IC technology for a given number of active device layers and methodology of partitioning across device layers for various technology nodes.

• 3DFP --- 3DFP is a thermal-aware floorplanner for the design of three-dimensional (3D) ICs. It takes into account the power dissipation of microarchitectural modules and interconnects, performs thermal-aware floorplanning across multiple layers in 3D ICs, and generates floorplans with balanced thermal profile, optimized interconnect length, and minimized silicon area.

Selected Publications:

• [GLSVLSI14] Tao Zhang, Cong Xu, Ke Chen, Guangyu Sun, Yuan Xie, "3D-SWIFT: A high-performance 3D-stacked Wide IO DRAM ", Proc. GreatLake Symposium on VLSI (GLSVLSI), Best Paper Award
• [GLSVLSI14] Qiaosha Zou, Tao Zhang, Cong Xu, Yuan Xie, "TSV Power Supply Array Electromigration Lifetime Analysis in 3D IC ", Proc. GreatLake Symposium on VLSI (GLSVLSI), 2014
• [SLIP14] Qiaosha Zou, Yuan Xie, "Compact Models and Model Standard for 2.5D and 3D Integration ", Proc. The 16th ACM/IEEE System Level Interconnect Prediction 2014 workshop, 2014
• [DAC14] Wulong Liu, Guoqing Chen, Xue Han, Yu Wang, Huazhong Yang, Yuan Xie, " Design Methodologies for 3D Mixed Signal Integration Circuits: A Practical 12-bit SAR ADC Design Case ", Proc. Design Automation Conferene (DAC), 2014
• [TCAD2013] Yibo Chen, Eren Kursun, Dave Motschman, Charles Johnson, Yuan Xie. "Through Silicon Via aware Design Planningfor Thermally-efficient 3D Integrated Circuits " IEEE Transactions on Computer Aids Design (TCAD)., pp.1335-1346, Vol.32, No. 9, Sept. 2013.
• [3DIC'10] Tao Zhang, Kui Wang, Yi Feng, Yan Chen, Qun Li, Bing Shao, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, and Youn-Long Lin "A 3D SoC Design for H.264 Application With On-Chip DRAM Stacking", to appear in the IEEE International 3D System Integration Conference (3DIC), Nov. 2010, Munich, Germany
• [3DIC'10] Jing Xie, Xiangyu Dong, Yuan Xie, "3D Memory Stacking for Fast Checkpointing/Restore Applications", IEEE International 3D System Integration Conference (3DIC), Nov. 2010, Munich, Germany
• [ICCAD'10] Yibo Chen, Dimin Niu, Yuan Xie, Krish Chakrabarty, Cost-Effective Integration of Three-Dimensional (3D) ICs Emphasizing Testing Cost Analysis, To Appear in ACM/IEEE Intl. Conf. on CAD (ICCAD), Nov. 2010.
• [ITC'10] L. Jiang, Y. Liu, L. Duan, Y. Xie and Q. Xu, "Modeling TSV Open Defects in 3D-Stacked DRAM", Proc. IEEE International Test Conference (ITC), paper 6.1, Nov. 2010.
• [SC10] Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman Jouppi. "Simple but Effective Heterogeneous Main Memory with On-chip Memory Controller Support." To appear in Proceedings of Supercomputing (SC 2010), November, 2010.
• [CICC'10] Tao Zhang, Kui Wang, Yi Feng, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, and Youn-Long Lin, "A Customized Design of DRAM Controller for On-Chip 3D DRAM Stacking", in the IEEE Custom Integrated Circuits Conference (CICC), Sep. 2010, San Jose, CA.
• [ISLPED10] Yibo Chen, Jishen Zhao, Yuan Xie, "3D-NonFAR: Three-Dimensional Non-Volatile FPGA ARchitecture Using Phase Change Memory", Internaitonal Symposium on Lower Power Electronics Design (ISLPED), 2010
• [IEEE MICRO] Gabe Loh and Yuan Xie, "3D Stacked Microprocessor: Are We There Yet?", IEEE Micro, Vol.30, No. 3, pp.60-64, May-June, 2010.
• [Microelectronics] Xiaoxia Wu, Yibo Chen, Krish Chakrabarty, Yuan Xie, "Test-Access Mechanism Optimization for Core-Based 3D SoCs" , Microelectronics Journal, Vol.41, pp.601-615, July, 2010.
• [DAC10] Jishen Zhao, Xiangyu Dong, Yuan Xie, "Cost-Aware Three-Dimensional (3D) Many-Core Multiprocessor Design." Proceedings of Design Automation Conference (DAC), pp. 126-131, 2010.
• [DAC10] Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Jian Li, Chita R. Das "Cost-driven 3D Integration with Interconnect Layers." Proceedings of Design Automation Conference (DAC). pp. 150-155, 2010.
• [TACO] Xiaoxia Wu, Jian Li, Lixi Zhang, E. Speight, R. Rajamony, Yuan Xie. "Hybrid Cache Architecture with Disparate Memory Technologies." To appear in ACM Transactions on Architecture and Code Optimization (TACO).
• [VLSID 10] Yuan Xie, "Processor Architecture Design Using 3D Integration Technology.(Invited Tutorial Paper)" Proceedings of VLSI Design. 2010.
• [ASPDAC10] Paul Falkstern, Yao-wen Chang, Yuan Xie, Yu Wang, "Three Dimensional Integrated Circuit (3D IC) Floorplan and Power/Ground Network Co-synthesis." Proceedings of Asia and South-Pacifc Design Automation Conference (ASP-DAC), 2010.
• [JETC] Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie. "Scan-Chain Design and Optimization for Three-Dimensional Integrated Circuits", ACM Journal on Emerging Technologies in Computing systems (JETC), 5-2, Article 9, 2009.
• [SC09] Xiangyu Dong, Naveen Muralimanohar, Norm Jouppi, Richard Kaufmann, Yuan Xie, "Leveraging 3D PCRAM Tech nologies to Reduce Checkpoint Overhead for Future Exascale Systems." Proceedings of International Conference on High Performance Computing, Networking, Storage and Analysis (SC). 2009.
• [ISCA 09] Xiaoxia Wu, Jian Li, Lixi Zhang, Evan Speight, Ram Rajamony, Yuan Xie, "Hybrid Cache Architecture with Disparate Memory Technologies.", In Proceedings of International Symposium on Computer Architecture (ISCA), June, 2009.
  
  
• [HPCA 09] Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen, "A Novel 3D Stacked MRAM Cache Architecture for CMPs", International Symposium on High Performance Computer Architecture, 2009 (35 out of 185 submissions, 19%).
  
  
• [ICCD 09] Al Maashri, A., G. Sun, X. Dong, V. Narayanan, Y. Xie. 3D GPU Architecture using Cache Stacking: Performance, Cost, Power, and Thermal Analysis. Proc. of International Conference on Computer Design (ICCD).
• [MTDT09] Balaji Vaidyanathan, Yu Wang, Yuan Xie, "Cost-Aware Lifetime Yield Analysis of Heterogeneous 3D On-chip Cache", IEEE International Workshop on Memory Technology, Design and Test, pp. 65-70, 2009.
• [3DIC09] Jin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, and Mary Jane Irwin, "Arithmetic Unit Design Using 180nm TSV-based 3D Stacking", IEEE International 3D System Integration Conference (3DSiC), 2009
• [ASPDAC 09] Xiangyu Dong, Yuan Xie, "System-level Cost Analysis and Design Exploration for 3D ICs", Asia and South Pacific Design Automation Conference, 2009. (Best Paper Nomination)
  
  
• [ASPDAC09] Sridharan, S., M. DeBole, G. Sun, Y. Xie, N. Vijaykrishnan. "A Criticality-Driven Microarchitectural Three Dimensional (3D) Floorplanner". Asia and South Pacific Design Automation Conference (ASP-DAC 2009). pp. 763-768.
• [ICCD 08] Xiaoxia Wu, Yibo Chen, K. Chakrabarty, Yuan Xie, "Test-Access Mechanism Optimization for Core-Based Three-Dimensional SOCs", International Conference on Computer Design, 2008.
  
  
• [ISCA 08] D. Park, S. Eachempati, R. Das, A. Mishra, Yuan Xie, V. Narayanan, C. Das, "MIRA: A Multi-layer On Chip Interconnect Router Architecture" [PDF] , Proceedings of Annual International Symposium on Computer Architecture (ISCA), pp. 251-261, June 2008.
• [DAC 08] Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Helen Li, Yiran Chen, Yuan Xie. "Circuit and Mircoarchitecture Evaluation of 3D Stacking Magnetic RAM (MRAM) as a Universal Memory Replacement" [PDF] , Proceedings of Design Automation Conference (DAC) 2008.
• [ITSW 08] Xiaoxia Wu, P. Falkenstern, K. Chakrabarty, Yuan Xie, "Scan-chain Design and Optimization for 3D ICs", International Test Syntehsis Workshop, 2008.
  
  
• [TVLSI08] Yuh-fang Tsai, Feng Wang, Yuan Xie, N. Vijaykrishnan, M. J. Irwin. "Design Space Exploration for Three-Dimensional Cache"[PDF]. IEEE Transactions on VLSI, pp.444-455, Vol.16, No.4, April 2008.
  
  
• [ICCD07] Xiaoxia Wu, Paul Falkenstern, and Yuan Xie. "Scan Chain Design for Three-dimensional (3D) ICs." [PDF] ; Proceedings of International Conference on Computer Design (ICCD), pp. 208-214, Oct. 2007.
  
  
• [IEEE-Micro] Gabriel Loh, Yuan Xie, and Bryan Black. "Processor Design in Three-Dimensional Die-Stacking Technologies."[PDF]; IEEE Micro, Vol. 27. No. 3, pp.31-48, May/June 2007.
  
  
• [ISCA07] Kim, J., C. Nicopoulos, D. Park, R. Das,Yuan  Xie, N. Vijaykrishnan, C. R. Das."A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures." [PDF]; Proceedings of the Annual International Symposium on Computer Architecture (ISCA), pp. 138-149, June 2007. (46 papers accepted out of 204 submissions. 23% acceptance rate)
  
  
• [VLSID07] B. Vaidyanathan., W-L. Hung, F. Wang, Yuan Xie, N. Vijaykrishnan, M. J. Irwin."Architecting Microprocessor Components in 3D Design Space." [PDF]; Proceedings of IEEE International Conference on VLSI Design (VLSID), pp. 103-108, Jan. 2007.
  
• [JETC06] Yuan Xie, Gabriel Loh, Bryan Black, and Kerry Bernstein,  "Design Space Exploration for 3D Architecture."[PDF]; ACM Journal of Emerging Technologies for Computer Systems, Vol. 2. No. 2, pp.65-103, April 2006.
  
• [ISCA06] F. Li, C. Nicopoulos, T. Richardson, Yuan Xie, N. Vijaykrishnan, and M. Kandemir, "Design and Management of 3D Chip Multiprocessors using Network-in-memory." [PDF 670KB]; Proceedings of the Annual International Symposium on Computer Architecture (ISCA), pp. 130-141, June. 2006. (31 papers accepted out of 234 submissions. 13% acceptance rate)
  
  
• [ISQED06] W.-L. Hung, G. Link, Yuan Xie, N. Vijaykrishnan, and M. J. Irwin"Interconnect and Thermal-aware Floorplanning for 3D Microprocessors." [PDF];Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 98-104, March. 2006.
  
  
• [ASPDAC06] O. Ozturk, Feng Wang, M. Kandemir, Yuan Xie, "Optimal Topology Exploration for Application-Specific 3D Architectures." [PDF]; Proceedings of Asia and South Paci¯c Design Automation Conference (ASP-DAC), pp. 390-395, Jan. 2006.
  
  
• [ICCD05] Y-F. Tsai, Yuan  Xie, N. Vijaykrishnan,and Mary J. Irwin,  "Three-Dimensional Cache Design Exploration Using 3DCacti." [PDF]; Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 519-524, Oct. 2005.
  
  

Tutorial:   

• Gabe Loh and Yuan Xie (Organizers), 3D tutorial at International Sympsoium on Computer Architecture (ISCA) 2008, Beijing, China. Click here for a copy of handout
  
  
• Alam Syed, Mike Ignatowski, Yuan Xie, 3D tutorial at Great Lake Symposium on VLSI, 2008, Orlando, FL.
  
  
• K. Bernstein, B. Black, G. Loh, Y. Xie, 3D Tutorial at  International Symposium on Microarchitecture (MICRO 2006), Click here for a copy of handout

Invited Talks on 3D IC:

02/2009	Semiconductor Research Corporations (SRC) .	Raleigh, NC
	" 3D IC Design and Architecture"
02/2009	Duke University.	Durham, NC
	" 3D IC Design and Architecture"
09/2008	Univ. of Texas in Austin.	Austin, TX
	" 3D EDA and Architecture"
09/2008	IBM Austin Research Labs.	Austin, TX
	" 3D EDA and Architecture"
09/2008	Freescale.	Austin, TX
	" 3D EDA and Architecture"
11/2007	Qualcomm.	San Diego, CA
	" 3D EDA and Architecture"
10/2007	Seagate Technology LLC.	Bloomington, MN
	" 3D IC Design Tutorial"
10/2007	SEMATECH 3D workshop	Albany, New York
	"3D Archtecture Design"
09/2007	KAIST University	Daejeon, Korea
	"Design Space Explorations for 3D ICs"
05/2007	Honda Research Institute.	Tokyo, Japan
	"Design Automation for Three-dimensional ICs"
05/2007	Peking University	Beijing, China
	"New Dimension for High Performance"
04/2007	IMEC (Interuniversity Microelectronics Centre)	Leuven, Belgium
	"The Challenges of Designing 3D Microarchitectures"
01/2007	Dagstuhl Seminar on Power-Aware Computing Systems.	Dagstuhl, Germany
	"Thermal Challenges in 3D Microarchitecture Design"
11/2006	The 3rd Annual 3D Architecture Conference.	San Francisco, CA
	"Design Space Exploration for 3D IC Design;
10/2006	University of Pittsburgh.	Pittsburgh, PA
	"The Challenges of Designing 3D Microarchitectures"
08/2006	Hongkong University of Science and Technology	Hong Kong, China
	"3D Microarchitecture Design"
08/2006	Intel China Research Center	Beijing, China
	"3D Microarchitecture Design"
03/2006	IBM T.J.Watson Research Center.	Yorktown, NY
	"The Challenges of Designing 3D Microarchitectures"

 

Last Updated by Yuan Xie on 10/29/2009