Yuan Xie's 3D IC Research Page

    A three dimensional (3D) chip is a stack of multiple device layers with direct vertical interconnects tunneling through them. A key benefit of this approach over a traditional two dimensional chip is the ability to reduce the length of long interconnects. Prior efforts have focused on developing different fabrication techniques involved in stacking multiple device layers and in forming the vertical interconnects. The size and density of the vertical interconnects that can tunnel between the different device layers varies based on the underlying technology used to fabricate the 3D chips.  To efficiently exploit the benefits of 3D technologies, design techniques and methodologies for supporting 3D designs are imperative.

Our 3D IC research projects were supported by NSF, SRC, DOE, DARPA, IBM, Qualcomm, and ITRI, with 3D chip fabrication supported by MITLL, Tezzaron, and IMEC.

New: The book "Three-dimensional IC: Design, CAD, and Architecture" edited by Yuan Xie, Jason Cong, Sachin Sapatnekar is published by Springer.

Tool Release:

  • 3DCACTI --- 3DCACTI is a tool for estimating the optimum access times, and power dissipation of a cache using 3D IC technology for a given number of active device layers and methodology of partitioning across device layers for various technology nodes.
  • 3DFP --- 3DFP is a thermal-aware floorplanner for the design of three-dimensional (3D) ICs. It takes into account the power dissipation of microarchitectural modules and interconnects, performs thermal-aware floorplanning across multiple layers in 3D ICs, and generates floorplans with balanced thermal profile, optimized interconnect length, and minimized silicon area.

Selected Publications: