Embedded System Design
Current projects in embedded system design area:
- Process Variation Aware Embedded MPSoC Synthesis, supported by NSF CAREER 0643902
- Embedded System Timing Analysis, supported by NSF CSR-EHS 0720659
- CSR: Medium: Collaborative Research: Providing Predictable Timing for Task Migration in Embedded Multi-Core Environments (TiME-ME), supported by NSF CSR-EHS 0905365
Embedded systems are of great economic importance. Embedded applications include consumer electronics appliance, signal processing, automobile control, aircraft autopilot, and so on. It is estimated that the embedded system market sales was approximately $46 billion in 2004 and expected to grow at an average rate of 14% over the next five years to reach $88 billion by 2009. Compared to general-purpose computing systems, embedded systems are more cost sensitive and require shorter time-to-market. To reduce the design effort and the cost of the system and shorten the time-to-market, the designer has to come up with a heterogeneous system, which usually consists of embedded processors and ASICs. Most embedded systems are heterogeneous multiprocessors with several different types of processing elements, including customized hardware processing elements as well as programmable CPUs, and hardware/software co-design is necessary to design embedded systems.
As a member of the Embedded System Group at Princeton University, Dr. Xie started to work in the area of embedded system-level synthesis and modeling, with a sponsorship from Mentor Graphics. He developed a hardware/software co-synthesis tool ASICosyn, and the co-synthesis techniques were integrated into a platform-based SOC design flow.
Selected publication in Hardware/software Co-synthesis:
- Y. Xie, J. Xu, W. Wolf. March 2003. Augmenting Platform-based Design with Synthesis Tools. Journal of Circuits, Systems and Computers, Vol. 12, No. 2 (2003) pp. 125-142
- Y. Xie, W. Wolf. Allocation and Scheduling of Conditional Task Graphs in Co-synthesis. Proceedings of the Design Automation and Test in Europe (DATE 2001). pp. 620-625. Munich, Germany.
- Y. Xie, W. Wolf. Co-synthesis with Custom ASICs. Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC 2000). pp. 129-134. Yokohama, Japan.
Embedded systems are space and cost sensitive and memory is one of the most restricted resources. The memory constraint on embedded systems has lead to the development of many code compression techniques. One such example is the IBM PowerPC 405 platform based System-on-a-chip design, in which instructions are compressed and stored in the memory, and a small decompression core called CodePack is put between the PLB (processor local bus) and the embedded PowerPC 405 processor to decompress instructions. Dr. Xie's Ph.D. thesis focused on code compression algorithms and decompression architecture design for VLIW-based SoCs, which is funded by SRC (Semiconductor Research Corporation). He proposed code compression algorithms and decompression architecture designs that can minimize performance degradation and help reduce the instruction bus power consumption. This research prject resulted in two patent applications, and SRC Inventor Recognition award in 2002. A test chip was fabricated through MOSIS using TSMC 0.25 um technology.
Selected publication in Code Compression Architecture for Embedded Systems:
Y. Xie, W. Wolf, H. Lekatsas. Profile-driven Code Compression. Proceedings of the Design Automation and Test in Europe (DATE 2003). pp. 462-467. Munich, Germany.
Y. Xie, W. Wolf, H. Lekatsas. Code Compression for VLIW Using Variable-to-fixed Coding. Proceedings of Fifteenth International Symposium on System Synthesis (ISSS 2002). Kyoto, Japan.
Y. Xie, W. Wolf, H. Lekatsas. A Code Decompression Architecture for VLIW Processors. Proceedings of the Thirty-Fourth International Symposium on Microarchitecture (MICRO-34). pp. 66-75. Austin, TX.
Industrial ASIC and SOC design Experience: After graduation from Princeton, Dr. Xie took a job as an Advisory Engineer in the SOC design and methodology group, World-Wide design center in the IBM Microelectronics division. Working as a design engineer, he was involved with several ASIC and SOC chip designs and the development of RTL handoff methodology. The design experience at IBM has helped him achieve a better understanding of the state-of-the-art design methodologies and the future technology challenges. It also motivated him to look at the reliability and temperature issues in embedded system design. After joining Penn State, he and his students further extended the previous work to take into consideration these issues.
Selected publication in Reliability-aware/Thermal-aware Embedded System Design:
W. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. Thermal-Aware Allocation and Scheduling for Systems-on-a-Chip Design. Proceedings of the Design, Automation, and Test in Europe (DATE 2005). Munich, Germany.
Tosun, S., N. Mansouri, E. Arvas, M. Kandemir, Y. Xie. Reliability-Centric Hardware/Software Co-design. Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED 2005). San Jose, CA.
Y. Xie, L.Li, N.Vijaykrishnan, M. Kandemir, M. J. Irwin, "Reliability-Aware Co-synthesis for Embedded Systems" , IEEE 15th International Conference on Application-specific Systems, Architectures and Processor (ASAP 2004). Galveston, Texas, September 27-29, 2004
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