The challenges in fabricating transistors with diminutive feature sizes in the nanometer regimes have resulted in significant variations in key transistor parameters, such as transistor channel length, gate-oxide thickness, and threshold voltage. This manufacturing variability can  cause significant performance and power deviations from nominal values in identical hardware designs. Designing for the worst case scenario may no longer be a viable solution, especially when the variability encountered in the new process technologies becomes very significant and causes substantial percentage deviations from the nominal values. Increasing cost sensitivity in the embedded system design methodology makes designing for the worst case infeasible. Further, worst-case analysis without taking the probabilistic nature of the manufactured components into account can also result in an overly pessimistic estimation in terms of performance.  As a result, a shift in the design paradigm, from today’s worst-case deterministic design to statistical or probabilistic design, is critical for deep sub-micron VLSI design.

The goal of the project includes:

• EDA solutions: developing design automation techniques to perform statistical analysis and variation-aware synthesis for nanometer VLSI systems.
• Circuit/Architecture solutions: developing design techniques for variation tolerant circuits/architecture.

Project Sponsors:

• NSF CAREER: Process Variation Aware Embedded MPSoC Synthesis

• SRC: Statistical Behavioral Synthesis for Nanometer VLSI Chips
  

Students:

• Feng Wang (Graduated in 2008, now with Qualcomm)
  
  
• Balaji Vaidyanathan (Graduated in 2009, now with TSMC)

• Yibo Chen

• Dimin Niu

Selected Publications:

• Yibo Chen, Yu Wang, Yuan Xie, Andres Takach, "Parametric Yield Driven Resource Binding in Behavioral Synthesis with Multi-Vth/Vdd Library." To appear in Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC). 2010.

• Yibo Chen, Yu Wang, Yuan Xie, Andres Takach, "Minimizing Leakage Power in Aging-Bounded High-level Synthesis with Design Time Multi-Vth Assignment." To appear in Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC). 2010.

• Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang. "Leakage Power and Circuit Aging Optimization by Gate Replacement Techniques." To appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI).

• Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie, "Intrinsic NBTI-Variability Aware Statistical Pipeline Performance Assessment and Tuning." Proceedings of International Conference on Computer-Aided Design (ICCAD). 2009. pp 164-171.

• Yuan Xie and Yibo Chen. "Statistical High Level Synthesis Considering Process Variations." IEEE Computer Design and Test, Special Issue on HLS, Vol. 26, Issue 4, pp.78-87, July-August, 2009.

• Hong Luo, Yu Wang, Rong Luo, Huazhong Yang, Yuan Xie. "Temperature-aware NBTI Modeling Techniques in Digital Circuits." IEICE Transactions on Electronics., No. 6, pp. 875-886, 2009.

• M. DeBole, R. Krishnan, V. Balakrishnan, W. Wang, H. Luo, Y. Wang, Y. Xie, Y. Cao and N. Vijaykrishnan. "New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components." International Journal of Parallel Programming., Vol. 37, No.4, pp.417-431, August, 2009.

• M. Mutyam, A. Mupid, F. Wang, N. Vijaykrishnan, Yuan Xie, M. Kandemir. "Process Variation Aware Adaptive Cache Architecture and Management." IEEE Transactions on Computers., Vol. 58, No.7, pp.865-877, July, 2009.

• R. Rajaraman, V. Degalahal, J. S. Kim, N. Vijaykrishnan, Y. Xie, M. J. Irwin. "Modeling Soft Errors at Device and Logic Level for Combinational Circuits." IEEE Transactions on Dependable and Secure Computing (TDCS)., Vol. 6, No. 3, pp.202-216, June 2009.

• B. Vaidyanathan, Y. Wang, Y. Xie, "Cost-Aware Lifetime Yield Analysis of Heterogeneous 3D On-Chip Cache", 2009 IEEE International Workshop on Memory Technology, Design, and Testing, pp.65-70, 2009.

• Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang. "Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization." Proceedings of Design Automation and Test in Europe (DATE), pp. 324-333. 2009.

• Feng Wang, Andres Takach, Yuan Xie. "Variation Aware Resource Binding and Scheduling."; in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) Jan. 2009.

• Yibo Chen, Yuan Xie. "Tolerating Process Variations in High-Level Synthesis Using Transparent Latches."; in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)Jan. 2009.
  
  
• Feng Wang, Guangyu Sun, Yuan Xie. "A Variation Aware High Level Synthesis Framework."; in Proceedings of Design Automation and Test in Europe (DATE), Mar. 2008.
  
  
• Feng Wang, Xiaoxia Wu, Yuan Xie. "Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning."; To appear in Proceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), Jan. 2008. Best Paper Award
  
  
• Feng Wang, C. Nicopoulos, Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan. "Variation-aware Task Allocation and Scheduling for MPSoC." Proc. of Intl. Conf. on Computer Aided Design (ICCAD), pp.138-149, Nov. 2007
  
  
• S. Srinivasan, P. Mangalagiri, Yuan Xie, N. Vijaykrishnan. "FPGA Routing Architecture Analysis Under Variations." Proceedings of International Conference on Computer Design (ICCD), pp. 152-157, Oct. 2007.
  
  
• Feng Wang, Yuan Xie, and Hai Ju. "A Novel Criticality Computation Method in Statistical Timing Analysis." Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 1611-1616, 2007.
  
  
• Wei-lun Hung, XiaoxiaWu, Yuan Xie. "Guaranteeing Performance Yield in High-Level Synthesis." Proceedings of Interna tional Conference on Computer Aided Design (ICCAD), pp.303-309, Nov. 2006. Best Paper Award Nomination

Note: Please click Full Publication List for a PDF version of any papers

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Last Updated by Yuan Xie on 12/6/2009