Bibliographic Citations

      


Behrooz Parhami: 2007/06/19 ||  E-mail: parhami@ece.ucsb.edu  ||  Problems: webadmin@ece.ucsb.edu

Other contact info at: Bottom of this page  ||  Go up to: Appendices to B. Parhami's CV or his home page

      

On June 19, 2007, Professor Parhami's UCSB ECE website moved to a new location. For an up-to-date version of this page, visit it at the new address: http://www.ece.ucsb.edu/~parhami/appB_bib_cites.htm

This Appendix B to B. Parhami's CV contains a partial list of citations of Professor Parhami’s work by other scholars. Numbers in brackets refer to items in his list of publications.

[AbuG99]

Abu-Ghazaleh, N. and P.A. Wilsey, “Managing Control Synchrony on SIMD Machines – A Survey,” Advances in Computers, ed. by M. Zelkovitz, 1999, pp. 240-303. Cites the 1995 paper on SIMD machines [105].

[Aiel01]

Aiello, W., S.N. Bhatt, F.R.K. Chung, A.L. Rosenberg, and R.K. Sitaraman, “Augmented Ring Networks,” IEEE Trans. Parallel and Distributed Systems, Vol. 12, No. 6, pp. 598-609, June 2001. Cites the 1996 SPDP paper on PRC rings [131].

[Akop97]

Akopian, D.A., O. Vainio, S.S. Agaian, and J.T. Astola, “SBNR Processor for Stack Filters,” IEEE Trans. Circuits and Systems II, Vol. 44, No. 3, pp. 197-208, March 1997. Cites the 1988, 1990, and 1993 papers on GSD arithmetic [56], [66], [86].

[Ali96]

Ali, A. and R. Vaidyanathan, “Exact Bounds on Running ASCEND/DESCEND and FAN-IN Algorithms on Synchronous Multiple-Bus Networks,” IEEE Trans. Parallel and Distributed Systems, Vol. 7, No. 8, pp. 783-790, August 1996. Cites the 1993 IEEETPDS paper on meshes with row/column buses [90].

[Amin06]

Amin, A., “High-Speed Self-Timed Carry-Skip Adder,” IEE Proc. Circuits,Devices, and Systems, Vol. 153, No. 6, pp. 574-582, December 2006. Cites the computer arithmetic book [179].

[Ande75] Anderson, J.A. and G.J. Lipovski, A Virtual Memory for Microprocessors, Proc. 2nd Symp. Computer Architecture, pp. 80-84, Jan. 1975. Cites the 1972 RAPID paper [2].
[Ante05] Antelo, E., T. Lang, P. Montuschi, and A. Nannarelli, “Digit-Recurrence Dividers with Reduced Logical Depth,” IEEE Trans. Computers, Vol. 54, No. 7, pp. 837-851, July 2005. Cites the 2003 IEEETC paper on high-radix division [207].

[Arms93]

Armstrong, J.R. and F.G. Gray, Structured Logic Design with VHDL, Prentice Hall, 482 pp., 1993, ISBN = 0-13-855206-1. Contains an extensive description of URISC on pp. 240-251. Mentions that the design is due to Mavaddat and Parham (sic), but does not list the 1988 URISC paper [54] among references.

[Arms00]

Armstrong, J.R. and F.G. Gray, VHDL Design Representation and Synthesis, 2nd Ed., Prentice Hall, 651 pp., 2000, ISBN = 0-13-021670. Contains an extensive description of URISC on pp. 245-257. Mentions that the design is due to Mavaddat and Parham (sic), but does not list the 1988 URISC paper [54] among references.

[Baja04] Bajard, J.-C., and T. Plantard, “RNS Bases and Conversions,” Advanced Signal Processing Algorithms, Architectures, and Implemenatations XIV (Proc. SPIE Conf. 5559), August 2004, pp. 60-69. Cites the 1993 Asilomar Conf. paper on optimal RNS conversions [91] and the 1994 CAM on approximate sign detection [92].
[Bein04] Bein, D., W.W. Bein, and S. Latifi, “Optimal Embedding of Honeycomb Networks into Hypercubes,” Parallel Processing Letters, Vol. 14, Nos. 3-4, pp. 367-375, 2004. Cites the 2001 IEEETPDS paper on honeycomb and diamond networks [191].
[Beiu04] Beiu, V., and M. Sulieman, “Optimal Practical Perceptron Addition Application to Single Electron Technology,” Proc. International Conf. VLSI, Las Vegas, NV, June 21-24, 2004, pp. 541-547. Cites the 1999 and 2000 Asilomar Conf. papers on threshold circuits [174], [190].
[Berr74] Berra, P.B., "Some Thoughts on the Future of Associative Memories/Processors in the Solution of Data Base Management Problems," Proc. ACM SIGFIDET (now SIGMOD) Workshop on Data Description, Access, and Control, May 1974, pp. 463-476. Cites the 1972 RAPID paper [2].
[Beuc02] Beuchat, J.-L., and A. Tisserand, “Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices,” Proc. 12th Int’l Conf. Field-Programmable Logic and Applications, 2002, LNCS #2438, pp. 513-522. Cites the computer arithmetic book [179].
[Blun02] Blunden, B., Virtual Machine Design and Implementation in C/C++, Worldware Publishing, 2002. Cites the computer arithmetic book [179] on p. 148.

[Bora83]   

Boral, H. and D.J. DeWitt, “Database Machines: An Idea Whose Time Has Passed? -- A Critique of the Future of Database Machines,” in Database Machines, ed. By H.-O. Leilich and M. Missikoff, Springer-Verlag, 1983, pp. 166-?. Cites the 1972 RAPID paper [2].

[Bose84]   

Bose, B., “Two Dimensional ARC Codes,” Proc. Fault-Tolerant Computing Symp., pp. 324-329, 1984. Cites the IEEETC 1978 code paper [28].

[Bose84a]   

Bose, B., “Unidirectional Error Correction/Detection for VLSI Memory”, Proc. 11th Int'l Symp. Computer Architecture, pp. 242-244, Jan. 1984. Cites the IEEETC 1978 code paper [28].

[Bose87]   

Bose, B., “2-Dimensional Arithmetic Residue Check Codes,” Computers & Mathematics with Applications, Vol. 13, Nos. 5/6, pp. 547-554, 1987. Cites the IEEETC 1978 arith. code paper [28].

[Bron97]   

Bronnimann, H., I.Z. Emiris, V.Y. Pan, and S. Pion, “Computing Exact Geometric Predicates Using Modular Arithmetic with Single Precision”, Proc. 13th Symp. Computational Geometry, pp. 174-182, Aug. 1997. Cites the Computers & Math. 1994 paper on RNS sign detection [92].

[Brug93]

Bruguera, J.D., E. Antelo, and E.L. Zapata, “Design of a Pipelined Radix-4 CORDIC Processor”, Parallel Computing, Vol. 19, pp. 729-744, 1993.  Cites IEEETC 1988 recoded BSD paper [56].

[Bush76]

Bush, J.A., G.J. Lipovski, S.Y.W. Su, J.K. Watson, and S.J. Ackerman, “Some Implementations of Segment Sequential Functions,” Proc. 3rd Symp. Computer Architecture, pp. 178-185, Jan. 1976. Cites the 1972 RAPID paper [2].

[Cail74]

Caillouet, L.P. and B.D. Shriver, “An Integrated Approach to the Design of Fault Tolerant Computing Systems,” Conf. Record 7th Workshop Microprogramming, pp. 12-24, Sep. 1974. Cites Diagnostic and Microdiagnostic Techniques for Digital Systems,” unpublished lecture notes for a short course, UCLA, Mar. 1974. 

[Camp06] Campobello, G., and M. Russo, “A Scalable VLSI Speed/Area Tunable Sorting Network,” J. Systems Architecture, Vol. 52, No. 10, pp. 589-602, October 2006. Cites the 1995 Asilomar Conf. paper on accumulative parallel counters [107].
[Card83] Cardenas, A.F., F. Alavian, and A. Avizienis, "Performance of Recovery Architectures in Parallel Associative Database Processors," ACM Trans. Database Systems, Vol. 8, No. 3, pp. 291-323, September 1983. Cites the 1972 RAPID paper [2].
[Card00] Cardarilli, G.C., M. Re, R. Lojacono, and G. Ferri, “A Systolic Architecture for High-Performance Scaled Residue to Binary Conversion,” IEEE Trans. Circuits and Systems I, Vol. 47, No. 10, pp. 1523-1526, October 2000. Cites the 1995 IEEETC paper on approximate CRT decoding [108].
[Carl01] Carle, J., J.-F. Myoupo, and I. Stojmenovic, “Higher Dimensional Honeycomb Networks,” J. Interconnection Networks, Vol. 2, No. 4, pp. 391-420, December 2001. Cites the parallel processing book [162].

[Chan02]]   

Chang, Y.-T. and K.T. Cheng, “Self-Referential Verification of Gate-Level Implementations of Arithmetic Circuits,” Proc. 39th Design Automation Conf., pp. 311-316, June 2002. Cites the computer arithmetic book [179].

[Cho03] Cho, H.-J. and L.-Y. Hsu, “Generalized Honeycomb Torus,” Information Processing Letters, Vol. 86, No. 4, pp. 185-190, 2003. Cites the 2001 IEEETPDS paper on honeycomb and diamond networks [191].

[Choi02]

Choi, Y. and E.E. Swartzlander, Jr., “Design of a Hybrid Prefix Adder for Non-Uniform Input Arrival Times,” Advanced Signal Processing Algorithms, Architectures, and Implementations XII (Proc. SPIE Int’l Symp.), July 2002. Cites the computer arithmetic book [179].

[Cope73]

Copeland, G.P., G.J. Lipovski, and S.Y.W. Su, “The Architecture of CASSM,” Proc. 1st Symp. Computer Architecture, pp. 121-128, Dec. 1973. Cites the 1972 RAPID paper [2].

[Coto05] Cotofana, S., C. Lageweg, and S. Vassiliadis, “Addition Related Arithmetic Operations via Controlled Transport of Charge,” IEEE Trans. Computers, Vol. 54, No. 3, pp. 245-252, March 2005. Cites the computer arithmetic book [179].
[Croo07] Crookes, D., and M. Jiang, “Using Signed Digit Arithmetic for Low-Power Multiplication,” Electronics Letters, Vol. 43, No. 11, pp. 613-614, 24 May 2007. Cites the computer arithmetic book [179].
[Dany05] Danysh, A., and D. Tan, “Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit,” IEEE Trans. Computers, Vol. 54, No. 3, pp. 284-293, March 2005. Cites the computer arithmetic book [179].

[Davi84]   

Davis, W.A. and D.-L. Lee, “An Associative Memory Scheme”, Proc. Int'l Conf. Computers and Applications, Beijing, June 1984, pp. 17-23. Cites the Proc. IEEE 1973 survey [4].

[Davi86]   

Davis, W.A. and D.-L. Lee, “Fast Search Algorithms for Associative Memories”, IEEE Trans. Computers, Vol. 35, No. 5, pp. 456-461, May 1986. Cites the Proc. IEEE 1973 survey [4].

[Dawi96]

Dawid, H. and H. Meyr, “The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation Without Correcting Iterations,” IEEE Trans. Computers, Vol. 45, No. 3, pp. 307-318, March 1996. Cites the 1988, 1990, and 1993 papers on GSD arithmetic [56], [66], [86].}

[Dawi99]

Dawid, H. and H. Meyr, CORDIC Algorithms and Architectures, in Digital Signal Processing for Multimedia Systems, ed. by K.K. Parhi and T. Nishitani, Marcel Dekker, 1999, pp. 623-655. Cites the 1990 IEEETC GSD paper [66].

[DeCa04]

De Caro, D., E. Napoli, and A.G.M. Strollo, “Direct Digital Frequency Synthesizers with Polynomial Hyperfolding Technique,” IEEE Trans. Circuits and Systems II, Vol. 51, No. 7, pp. 337-344, July 2004. Cites the computer arithmetic book [179] as its reference [34].

[Deca05]

Decayeux, C., and D. Seme, “3D Hexagonal Network: Modeling, Topological Properties, Addressing Scheme, and Optimal Routing Algorithm,” IEEE Trans. Parallel and Distributed Systems, Vol. 16, No. 9, pp. 875-884, September 2005. Cites the parallel processing book [162].

[Deig81]   

Deighton, S. (Ed.), Computers in Developing Countries –– A Bibliography, IEE, London, 1981, Section 2.7.4. Cites the 1977 informatics in Iran paper [24].

[Desc06]   

Deschamps, J.-P., G.J.A. Bioul, and G.D. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems, Wiley-Interscience, 2006. Cites the computer arithmetic book [179] in Chapters 3, 5, 6, and 16.

[DeWi78]   

DeWitt, D.J., “DIRECT -- A Multiprocessor Organization for Supporting Relational Data Base Management Systems,” Proc. 5th Symp. Computer Architecture, pp. 182-189, Apr. 1978. Cites the 1972 RAPID paper [2].

[Dhil87]   

Dhillon, B.S., Reliability in Computer System Design, Ablex, 1987. Cites the 1974 AFIPS Conf. paper on fault-tolerant parallel DSP [8].

[Di03] Di, J., and J.S. Yuan, Power-Aware Pipelined Multiplier Design Based on 2-Dimensional Pipeline Gating, Proc. 13th ACM Great Lakes Symp. VLSI, April 2003, pp. 64-67. Cites the computer arithmetic book [179].
[Di06] Di, Jia, J.S. Yuan, and R. Demara (U Central Florida), “Improving Power-Awareness of Pipelined Array Multipliers Using Two-Dimensional Pipeline Gating and Its Application on FIR Design,” Integration: the VLSI Journal, Vol. 39, No. 2, pp. 90-112, March 2006. Cites the computer arithmetic book [179].
[Dimi05] Dimitrakopoulos, G., and D. Nikolos, “High-Speed Parallel-Prefix VLSI Ling Adders,” IEEE Trans. Computers, Vol. 54, No. 2, pp. 225-231, February 2005. Cites the computer arithmetic book [179].

[Dini99]

Dinitz, Y., S. Even, R. Kupershtok, and M. Zapolotsky, “Some Compact Layouts of the Butterfly,” Proc. 11th ACM Symp. on Parallel Algorithms and Architectures, pp. 54-63, June 1999. Cites a tech. report on layout and packaging of butterfly nets that led to the  SPAA 2000 paper [185].

[Drap01] Draper, B.A., A.P.W. Bohm, J. Hammes, W. Najjar, J.R. Beveridge, C. Ross, M. Chawathe, M. Desai, and J. Bins, “Compiling SA-C Programs to FPGAs: Performance Results,” Proc. 2nd Int’l Workshop Computer Vision Systems (Lecture Notes in Computer Science, Vol. 2095), 2001, pp. 220-235. Cites the computer arithmetic book [179].

[Erce94]

Ercegovac, M.D. and T. Lang, Division and Square Root: Digit-Recurrence Algorithms and Implementations, Kluwer, 1994. Cites the 1990 IEEETC GSD paper [66].

[Erce98]

Ercegovac, M.D. and T. Lang, “Effective Coding for Fast Redundant Adders Using the Radix-2 Digit Set {0, 1, 2, 3},” Proc. Asilomar Conf. Signals, Systems, and Computers, 1998, pp. 1163-1167. Cites the 1989 IPPS parallel multiplier paper [58].

[Erce04] Ercegovac, M.D. and T. Lang, Digital Arithmetic, Morgan Kaufmann, 2004. Cites five papers on table look-up for convergence division [50], addition of recoded BSD numbers [56], GSD support functions [86], pipelined multioperand addition [135], and fast tree multipliers [136], plus the computer arithmetic book [179].
[Even02] Even, S., and R. Kupershtok, “Layout Area of the Hypercube,” Proc. 13th ACM-SIAM Symp. Discrete Algorithms, January 2002, pp. 366-371. Cites the 1999 paper on VLSI layout of hypercubic networks [164].

[Fahm01]

Fahmy, H.A.H., A.A. Liddicoat, and M.J. Flynn, “Improving the Effectiveness of Floating-Point Arithmetic,” Proc. 35th Asilomar Conf. Signals, Systems, and Computers, Nov. 2001. Cites the 1993 IEEE TC paper on arithmetic support functions for GSD [86].

[Fahm02]

Fahmy, H.A.H., A.A. Liddicoat, and M.J. Flynn, “Parametric Time Delay Modeling for Floating Point Units,” Advanced Signal Processing Algorithms, Architectures, and Implementations XII (Proc. SPIE Int’l Symp.), July 2002. Cites the 1990 IEEETC GSD paper [66].

[Fahm03] Fahmi, H.A.H. and M.J. Flynn, “The Case for a Redundant Format in Floating-Point Arithmetic,” Proc. 16th IEEE Symp. Computer Arithmetic, June 2003, pp. 95-102. Cites IEEE TC 1990 paper on GSD [66] and 1993 paper on arithmetic support functions [86].
[Fan05] Fan, L.-J., C.-B. Yang, and S.-H. Shiau, “Routing Algorithms on the Bus-Based Hypercube Network,” IEEE Trans. Parallel and Distributed Systems, Vol. 16, No. 4, pp. 335-348, April 2005. Cites the 1993 IEEE TPDS paper on mesh with separable buses [90].
[Fan07] Fan, J., X. Jia, and X. Lin, “Optimal Embeddings of Paths with Various Lengths in Twisted Cubes,” IEEE Trans. Parallel and Distributed Systems, Vol. 18, No. 4, pp. 511-522, April 2007. Cites the 1999 IEEE TPDS paper on stable insertion sorter [163].

[Fars83]

Farsi, H. and J. Tartar, “A Relational Data Base Machine Employing Associative Memories and Transposed Files,” Proc. ACM Annual Conference Computers: Extending the Human Resource, pp. 193-199, Jan. 1983. Cites the Proc. IEEE 1973 survey paper [4].

[Faym99]

Fayman, J.A., P. Pirjanian, H.I. Christensen, and E. Rivlin, “Exploiting Process Integration and Composition in the Context of Active Vision,” IEEE Trans. Systems, Man and Cybernetics, Part C, Vol. 29, No. 1, pp. 73-86, February 1999. Cites the 1994 IEEETR paper on voting algorithms [101].

[Feng77]

Feng, T.-Y., “Guest Editorial: An Overview of Parallel Processors and Processing,” ACM Computing Surveys, Vol. 9, No. 1, pp. 1-2, Jan. 1977. Cites the Proc. IEEE 1973 survey paper [4].

[Frek97]

Freking, W.L. and K.K. Parhi, “Low-Power FIR Digital Filters Using Residue Arithmetic”, Proc. 31st Asilomar Conf. Signals Systems and Computers, Nov. 1997, pp. 739-743. Cites the 1996 Signal Processing paper on hybrid RNS-binary arithmetic [129].

[Frek99]

Freking, W.L. and K.K. Parhi, “Montgomery Modular Multiplication and Exponentiation in the Residue Number System”, Proc. 33rd Asilomar Conf. Signals Systems and Computers, Oct. 1999, pp. 1312-1316. Cites the 1994 IPL paper on RNS division [97] as a seminal work.

[Frek00]

Freking, W.L. and K.K. Parhi, “Modular Multiplication in the Residue Number System with Application to Massively-Parallel Public-Key Cryptography Systems,” Proc. 34th Asilomar Conf. Signals Systems and Computers, Oct. 2000, pp. 1339-1343. Cites the 1994 IPL paper on RNS division [97].

[Gait84]   

Gaitanis, N., “Totally Self Checking Checkers for Low Cost Arithmetic Codes”, Proc. Fault-Tolerant Computing Symp., pp. 260-264, 1984. Cites the IEEETC 1978 arithmetic error code paper [28].

[Garc03] Garcia, F., J. Solano, I. Stojmenovic, and M. Stojmenovic, “Higher Dimensional Hexagonal Networks,” J. Parallel and Distributed Computing, Vol. 63, pp. 1164-1172, 2003. Cites the 2001 IEEE TPDS paper on unified formulation of honeycomb and diamond networks [191].

[Gonz00]

Gonzalez, A.F. and P. Mazumdar, “Redundant Arithmetic, Algorithms and Implementations,” Integration: The VLSI Journal, Vol. 30, No. 1, pp. 13-53, Nov. 2000. Cites the 1990 IEEETC GSD paper [66] and uses it extensively for notation and examples.

[Grem02] Grembowski, T., R. Lien, K. Gaj, N. Nghi, P. Bellows, J. Flidr, T. Lehman, and B. Schott, “Comparative Analysis of the Hardware Implementation of Hash Functions SHA-1 and SHA-512,” Proc. 5th Int’l Conf. Information Security (Lecture Notes in Computer Science, Vol. 2433), 2002, pp. 75-89. Cites the computer arithmetic book [179].
[Hadj04] Hadjicostis, C.N., “Coding Techniques for Fault-Tolerant Parallel Prefix Computations in Abelian Groups,” Computer J., Vol. 47, No. 3, pp. 329-341, 2004. Cites the computer arithmetic book [179].

[Harw99]   

Harwood, A. and H. Shen, A Method of Trading Diameter for Reduced Degree to Construct Low Cost Interconnection Networks,” Proc. ACM Symp. Applied Computing, pp. 474-480, Feb. 1999. Cites the ICA3P 1996 paper on hier. fully connected nets [120] and the I-SPAN 1996 paper on hier. swapped nets [123].

[He06]

He, M., and W. Xiao, “A Unified Addressing Schema for Hexagonal and Honeycomb Networks with Isomorphic Cayley Graphs,” Proc. 1st Int’l Multisymp. on Computer and Computational Sciences, June 2006, Vol. 1, pp. 363-368. Cites the parallel processing book [162] and multiple papers on interconnection networks based on Cayley graphs [160], [191], [211]. 

[Heal76]

Healy, L.D., “A Character-Oriented Context-Addressed Segment-Sequential Storage,” Proc. 3rd Symp. Computer Architecture, pp. 172-177, Jan. 1976. Cites the 1972 RAPID paper [2]. 

[Hert79]   

Hertz, K.J., Review #27710, Mathematical Reviews, Vol. 58, p. 4083, July-Dec. 1979. Review of the 1976 RNS paper [14].

[High02]

Higham, N.J., Accuracy and Stability of Numerical Algorithms, SIAM, 2nd ed., 2002.  Cites the computer arithmetic book [179].

[Hill78]   

Hill, B., “Optical Memory Systems”, in Digital Memory and Storage, ed. by W.E. Proebster, Vieweg, Braunschweig, 1978, pp. 273-289. Cites the Proc. IEEE 1973 survey paper [4].

[Hill85]   

Hillis, W.D., The Connection Machine, MIT Press, 1985. Cites the 1972 RAPID paper [2].

[Hose04] HoseinNejad, R., A. Bab-Hadishahr, and P. Harding, “Fusion of Brake Pedal Sensors in by-Wire Cars: A Fuzzy Logic Approach,” Proc. 3rd IFAC Symp. Mechatronic Systems, Sydney, Australia, September 2004, pp. 639-644. Cites the 1994 IEEETR paper on voting algorithms [101].
[Hose05] Hoseiny Farahabady, M., and H. Sarbazi-Azad, “The Recursive Transpose-Connected Cycles (RTCC) Interconnection Network for Multiprocessors,” Proc. ACM Symp. Applied Computing, Santa Fe, NM, 2005, pp. 734-738. Cites the 1996 I-SPAN paper on swapped networks [123] and the 1999 IEEE TPDS paper on PRC rings [169].

[Hurs87]   

Hurson, A.R. and B. Shirazi, “Associative Memories: Has Their Time Come? Applications and VLSI Complexity”, Proc. Hawaii Int'l Conf. on System Sciences, 1987, pp. 284-292. Cites the Proc. IEEE 1973 survey paper [4].

[Imam05]

Imam, T., and M. Kaykobad, “A New Symbolic Substitution Based Addition Algorithm,” Computers and Mathematics with Applications, Vol. 50, Nos. 8-9, pp. 1303-1310, October 2005. Cites the 1990 IEEETC paper on GSD [66] and the book on computer arithmetic [179].

[Jino78]

Jino, M. and J.W.S. Liu, “Intelligent Magnetic Bubble Memories,” Proc. 5th Symp. Computer Architecture, pp. 166-174, Apr. 1978. Cites the 1972 RAPID paper [2].

[Jova02]

Jovanov, E., V. Milutinovic, and A.R. Hurson, “Acceleration of Nonnumeric Operations Using Hardware Support for the Ordered Table Hashing Algorithms,” IEEE Trans. Computers, Vol. 51,  No. 9, pp. 1026-1040, Sep. 2002. Cites the IEEETPDS 1999 paper on linear-array stable insertion sorter [163].}

[Kali04] Kaliski, R., A. Clarkson, and A.A. Lidicoat, “Self-Timed Adder Performance and Area Modeling,” Advanced Signal Processing Algorithms, Architectures, and Implemenatations XIV (Proc. SPIE Conf. 5559), August 2004, pp. 21-30. Cites the computer arithmetic book [179].

[Kang02]

Kang, C.Y. and E.E. Swartzlander, Jr., “A Constant-Delay MSB-First Bit-Serial Adder,” Advanced Signal Processing Algorithms, Architectures, and Implementations XII (Proc. SPIE Int’l Symp.), July 2002. Cites the computer arithmetic book [179].

[Kang02a] Kang, Y.K., D.W. Kim, T.W. Kwon, and J. R. Choi, “An Efficient Implementation of Hash Function Processor for IPSEC,” Proc. Third Asia-Pacific Conf. ASICs http://www.ap-asic.org/2002/2B-4.pdf, August 2002.Cites the computer arithmetic book [179].

[Kara01]

Karagianni, K., V. Paliouras, G. Diamantakos, and T. Stouraitis, “Operation-Saving VLSI Architectures for 3D Geomertical Transformations,” IEEE Trans. Computers, Vol. 50, No. 6, pp. 609-622, June 2001. Cites the computer arithmetic book [179].

[Karp80]   

Karpovsky, M., Review #68006, Mathematical Reviews, Vol. 1980b, p. 755, Feb. 1980. Review of the 1977 math. aspects of reliability survey [20].

[Kenn05] Kenney, R.D., and M.J. Schulte, “High-Speed Multioperand Decimal Adders,” IEEE Trans. Computers, Vol. 54, No. 8, pp. 953-963, August 2005. Cites the 1996 Asilomar Conf. paper on pipelined multioperand adders [135] and the computer arithmetic book [179].
[Khoo01] Khoo, K.-Y., Z. Yu, and A.N.Wilson, Jr., “Design of Optimal Hybrid Form FIR Filter,” Proc. IEEE Int’l Symp. Circuits and Systems, 2001, Vol. 2, pp. 621-624. Cites the computer arithmetic book [179].

[Kim00]

Kim, J. and E.E. Swartzlander, Jr., “Improving the Recursive Multiplier,” Proc. Asilomar Conf. Signals, Systems, and Computers, Oct. 2000, pp. 1320-1324. Cites the computer arithmetic book [179].

[Kise04] Kiselyov, O., and C.-c. Shan, “Functional Pearl: Implicit Configurations – or, Type Classes Reflect the Values of Types,” Proc. ACM SIGPLAN Workshop on Haskell, 2004, pp. 33-44. Cites the computer arithmetic book [179].

[Koho87]   

Kohonen, T., Content-Addressable Memories, Springer-Verlag, Berlin, 2nd Ed., 1987, pp. 4 & 166- 172. Extensively quotes from the Proc. IEEE 1973 survey [4] and cites the 1972 RAPID paper [2].

[Koho89]

Kohonen, T., “Content-Addressable Memory,” in Encyclopedia of Microcomputers, Vol. 4, Marcel Dekker, 1989, pp. 121-142. Cites the 1972 RAPID paper [2].

[Kore93] Koren, I., Computer Arithmetic Algorithms, Prentice Hall, 1993. Cites the 1990 IEEETC GSD paper [66].
[Kore02] Koren, I., Computer Arithmetic Algorithms, A.K. Peters, 2nd ed., 2002. Cites the computer arithmetic book [179] and the 1990 IEEETC GSD paper [66].
[Korn03] Kornerup, P., “Revisiting SRT Quotient Digit Selection,” Proc. 16th IEEE Symp. Computer Arithmetic, June 2003, pp. 38-45. Cites the 2001 Asilomar Conference paper on quotient digit selection [198].
[Korn05] Kornerup, P., “Digit Selection for SRT Division and Square Root,” IEEE Trans. Computers, Vol. 54, No. 3, pp. 294-303, March 2005. Cites the 2001 Asilomar Conf. paper on quotient digit selection [198].
[Korn06] Kornerup, P., and J.-M. Muller, “Leading Guard Digits in Finite Precision Redundant Representations,” IEEE Trans. Computers, Vol. 55, No. 5, pp. 541-548, May 2006. Cites the paper on arithmetic support functions for GSD [86].

[Krag01]   

Kragic, D., and H.I. Christensen, “Cue Integration for Visual Servoing,” IEEE Trans. Robotics and Automation, Vol. 17, No. 1, pp. 18-27, February 2001. Cites the 1994 IEEETR paper on voting algorithms [101].

[Krik94]   

Krikelis, A. and C.C. Weems, Associative Processing and Processors, IEEE Computer, pp. 12-17, Nov. 1994. Cites the Proc. IEEE 1973 survey paper [4].

[Lafr99]   

Lafruit, G., F. Catthoor, J.P.H. Cornelis, and H.J. De Man, “An Efficient VLSI Architecture for 2-D Wavelet Image Coding with Novel Image Scan,” IEEE Trans. VLSI Systems, Vol. 7, No. 1, pp. 56-68, March 1999. Cites the 1988 IEEETC paper on recoded BSD numbers [56].

[Land02]   

Landers, G., Y. Hovhannisyan, and V. Liu, Hardware Dividers Speed Communication Applications,Proc. Design Con, 2002. Cites the computer arithmetic book [179].

[Lati03] Latif-Shabgahi, G., S. Bennett, and J.M. Bass, “Smoothing Voter: A Novel Voting Algorithm for Handling Multiple Errors in Fault-Tolerant Control Systems,” Microprocessors and Microsystems, Vol. 27, pp. 303-313, 2003. Cites the 1994 IEEETR paper on voting algorithms [101].
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Lea, R.M. and E.J. Schuegraf, “An Associative File Store Using Fragments for Run-Time Indexing and Compression,” Proc. 3rd Annual ACM SIGIR Conf., Cambridge, UK, pp. 280-295, June 1980. Cites the 1972 RAPID paper [2] and the Proc. IEEE 1973 survey [4].

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Leilich, H.-O., “Access Methods and Associative Memories,” in Digital Memory and Storage, ed. by W.E. Proebster, Vieweg, Braunschweig, 1978, pp. 351-359. Cites the Proc. IEEE 1973 survey [4].

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Levitin, G., “Maximizing Survivability of Vulnerable Weighted Voting System,” Reliability Engineering & System Safety, Vol. 83, pp. 17-26, 2004. Cites the 1991 IPPS paper on voting networks [73] and the 1994 IEEETR paper on voting algorithms [101].

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Lin, C.S., D.C.P. Smith, and J.M. Smith, “The Design of a Rotating Associative Memory for for Relational Database Applications”, ACM Trans. Database Systems, Vol. 1, No. 1, pp. 53-65, Mar. 1976. Cites the 1972 RAPID paper [2].

[Lin00]

Lin, R., K. Nakano, S. Olariu, M.C. Pinotti, J.L. Schwing, and A.Y. Zomaya, “Scalable Hardware-Algorithms for Binary Prefix Sums,” IEEE Trans. Parallel and Distributed Systems, Vol. 11, No. 8, pp. 838-850, Aug. 2000. Cites the computer arithmetic book [179].

[Lin01]

Lin, R., “Reconfigurable Parallel Inner Product Processor Architectures,” IEEE Trans. VLSI Systems, Vol. 9, No. 2, pp. 261-272, Apr. 2001. Cites the computer arithmetic book [179].

[Lin03] Lin, R., K. Nakano, S. Olariu, and A. Zomaya, “An Efficient Parallel Prefix Sums Architectures with Domino Logic,” IEEE Trans. Parallel and Distributed Systems, Vol. 14, No. 9, pp. 922-931, September 2003. Cites the computer arithmetic book [179].

[Lipo76]

Lipovski, G.J., “A Question of Style,” Computer Architecture News, Vol. 5, No. 4, pp. 32-38, Oct. 1976. Cites the 1972 RAPID paper [2].

[Lipo78]

Lipovski, G.J., “Architectural Features of CASSM,” Proc. 5th Symp. Computer Architecture, pp. 31-38, Apr. 1978. Cites the 1972 RAPID paper [2].

[Liu95] Liu,J.-C., and K.G. Shin, Efficient Implementation Techniques for Gracefully Degradable Microprocessor Systems, IEEE Trans. Computers, Vol. 44, No. 4, pp. 503-517, April 1995. Cites the 1991 IEEE TR paper on voting networks [75].
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[Lu04] Lu, M., Arithmetic and Logic in Computer Systems, Wiley, 2004. Cites the IEEE TC 1990 paper on GSD [66] in Chapters 1 and 11.
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Marvel, O.E., “Happe Honeywell Associative Parallel Processing Ensemble,” Proc. 1st Symp. Computer Architecture, pp. 261-267, Dec. 1973. Cites the Proc. IEEE 1973 survey paper [4].

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Matsumae, S. and N. Tokura, “An Efficient Self-Simulation Algorithms for Reconfigurable Meshes,” Proc. 12th ACM Symp. on Parallel Algorithms and Architectures, pp. 216-223, July 2000. Cites the IEEE TPDS 1993 paper on meshes with row/column buses [90].

[Mats06]

Matsumae, S., “Tight Bounds on the Simulation of Meshes with Dynamically Reconfigurable Row/Column Buses by Meshes with Statically Partitioned Buses,” J. Parallel and Distributed Computing, Vol. 66, No. 10, pp. 1338-1346, October 2006. Cites the IEEE TPDS 1993 paper on meshes with row/column buses [90].

[Moha95] Mohapatra, P. and C.R. Das, “On Dependability Evaluation of Mesh-Connected Processors,” IEEE Trans. Computers, Vol. 44, No. 9, pp. 1073-1084, September 1995. Cites the 1993 IEEETPDS paper on meshes with row/column buses [90].
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Monakhov, O.G. and E.A. Monakhova, “A Class of Parametric Regular Networks for Multicomputer Architectures,” Computacion y Sistemas, Vol. 4, No. 2, pp. 85-93, 2000. On-line journal (ISSN 1405-5546): http://www.ejournal.unam.mx/compuysistemas/vol04-02/CYS04201.pdf. Cites the 1996 PPL paper on generalization of hypercubic networks [137] and the 1998 Computer J. paper on Gaussian Cubes [151].}

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Motsch, Walter, “Increased Chip Capacity and Extended Logical Complexity of LSI-Associative Memories”, in Digital Memory and Storage, ed. by W.E. Proebster, Vieweg, Braunschweig, 1978, pp. 361-375. Cites the 1973 Proc. IEEE survey paper [4].

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Mukhopadhyay, A., “Hardware Algorithms for Nonnumeric Computation,” Proc. 5th Symp. Computer Architecture, pp. 8-16, Apr. 1978. Cites the 1972 RAPID paper [2]. 

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[Mull06] Muller, J.-M., Elementary Functions: Algorithms and Implementation, Birkhauser, 2nd ed., 2006. Cites the 1988 IEEETC paper on recoded BSD [56], 1990 IEEETC paper on GSD [66], 1993 IEEETC paper on arithmetic support functions [86], and book on computer arithmetic [179].

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Nagendra, C., R.M. Owens, and M.J. Irwin, “Unifying Carry-Sum and Signed-Digit Number Representations for Low Power,” Proc. Int'l Symp. Low Power Design, pp. 15-20, Apr. 1995. Cites the 1990 IEEETC GSD paper [66].

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Nakano, K., S. Olariu, and A.Y. Zomaya, “Energy-Efficient Permutation Routing in Radio Networks,” IEEE Trans. Parallel and Distributed Systems, Vol. 12, No. 6, pp. 544-557, June 2001. Cites the parallel processing book [162].

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Nakano, K. and S. Olariu, “Uniform Leader Election Protocols for Radio Networks,” IEEE Trans. Parallel and Distributed Systems, Vol. 13, No. 5, pp. 516-526, May 2002. Cites the parallel processing book [162].

[Naka02a]

Nakano, K. and S. Olariu, “Leader Election Protocols for Radio Networks,” in Handbook of Wireless Networks and Mobile Computing, ed. by I. Stojmenovic, Wiley, New York, 2002, pp. 219-242. Cites the parallel processing book [162].

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Nakano, K., and Y. Yamagishi, “Hardware n Choose k Counters with Applications to the Partial Exhaustive Search,” IEICE Trans. Information and Systems, Vol. E88-D, No. 7, pp. 1350-1359, July 2007. Cites the computer arithmetic book [179].

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Nikolos, D., N. Gaitanis, and G. Philokyprou, “Systematic t-Error Correcting / All Unidirectional Error Detecting Codes,” IEEE Trans. Computers, Vol. 35, No. 5, pp. 394-402, May 1986. Cites the IEEETC 1978 arithmetic error code paper [28].

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Nordmann, L. and H. Pham, “Weighted Voting Systems,” IEEE Trans. Reliability, Vol. 48, No. 1, pp. 42-49, March 1999. Cites the 1991 voting complexity paper [76], the 1994 IJRQSE paper on threshold voting [94], and the 1994 IEEETR paper on voting algorithms [101].

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[Ozka77a] Ozkarahan, E., "Analysis of Architectural Features for Enhancing the Performance of a Database Machine," ACM Trans. Database Systems, Vol. 2, No. 4, pp. 297-316, December 1977. Cites the 1972 RAPID paper [2].

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Ozkarahan, E., Database Machines and Database Management, Prentice-Hall, 1986, pp. 220-221. Describes RAPID [2] in some detail.

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Paliouras, V. and T. Stouraitis, Low-Power Properties of the Logarithmic Number System, Proc. 15th Symp. Computer Arithmetic, June 2001, pp. 229-236. Cites the computer arithmetic book [179].

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Paliouras, V., A. Skavantzos, and T. Stouraitis, Multi-Voltage Low Power Convolvers Using the Polynomial Residue Number Systems, Proc. 12th Great Lakes Symp. VLSI, New York, pp. 7-11, Apr. 2002. Cites the computer arithmetic book [179].

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Paliouras, V., and T. Stouraitis, “Computer Arithmetic Techniques for Low-Power Systems,” in Designing CMOS Circuits for Low Power, ed. by D. Soudris, C. Piguet, and C. Goutis, Kluwer, 2002, pp. 97-116. Cites the computer arithmetic book [179].

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Pan, Y, S.Q. Zheng, K. Li, and H. Shen, “An Improved Generalization of Mesh-Connected Computers with Multiple Buses,” IEEE Trans. Parallel and Distributed Systems, Vol. 12, No. 3, pp. 293-305, Mar. 2001. Cites the IEEETPDS 1993 paper on meshes with row/col. buses [90].

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Papachristou, C.A., “Associative Table Lookup Processing for Multioperand Residue Arithmetic”, Journal of the ACM, Vol. 34, No. 2, pp. 376-396, Apr. 1987. Cites the Proc. IEEE 1973 survey paper [4].

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Patel, R.A., M. Benaissa, and S. Boussakata, “Efficient New Approach for Modulo 2n – 1 Addition in RNS,” IEE Proc. Computers and Digital Techniques, Vol. 153, No. 6, pp. 399-405, November 2006. Cites the computer arithmetic book [179].

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Patel, R.A., M. Benaissa, and S. Boussakta, “Fast Modulo 2n – (2n–2 + 1) Addition: A New Class of Adders for RNS,” IEEE Trans. Computers, Vol. 56, No. 4, pp. 572-576, April 2007. Cites the computer arithmetic book [179].

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Phatak, D.S. and I. Koren, “Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations with Bounded Carry Propagation Chains,” IEEE Trans. Computers, Vol. 43, No. 8, pp. 880-891, Aug. 1994. Cites the 1990 IEEETC GSD paper [66] and discusses the relationship between HSD and GSD representations in an appendix, referencing personal communication with B. Parhami.

[Phat98]

Phatak, D. S., S. Kahle, H. Kim, and J. Lue, “Hybrid Signed Digit Representation for Low Power Arithmetic Circuits,” Proc. Power-Driven Microarchitecture Workshop (in conjunction with ISCA), Barcelona, June 1998. Cites the 1990 IEEE TC GSD paper [66].

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Phatak, D.S., “Double Step Branching CORDIC: A New Algorithm for Fast Sine and Cosine Generation,” IEEE Trans. Computers, Vol. 47, No. 5, pp. 587-603, May 1998. Cites the 1990 IEEETC paper on GSD representations [66].

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Phatak, D.S., “Comment on Duprat and Muller’s Branching CORDIC Paper,” IEEE Trans. Computers, Vol. 47, No. 9, pp. 1037-1040, September 1998. Cites the 1990 IEEETC paper on GSD representations [66].

[Phat01]

Phatak, D. S., T. Goff, and I. Koren, “Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations,” IEEE Trans. Computers, Vol. 50, No. 11, pp. 1267-1278, Nov. 2001. Cites the 1990 IEEE TC GSD paper [66] and the computer arithmetic book [179].

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Phillips, B., “Modular Multiplication in the Montgomery Residue Number System,” Proc. 35th Asilomar Conf. Signals, Systems, and Computers, Nov. 2001. Cites the computer arithmetic book [179].

[Poon03] Poon, A.S.Y., D.N.C. Tse, and R.W. Brodersen, “An Adaptive Multiantenna Transceiver for Slowly Flat Fading Channels,” IEEE Trans. Communications, Vol. 51, No. 11, pp. 1820-1827, November 2003. Cites the computer arithmetic book [179].

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Pramanik, S., “Database Filters,” Proc. 9th Symp. Computer Architecture, pp. 201-210, Apr. 1982. Cites the 1972 RAPID paper [2].  

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Premkumar, A.B., “A Formal Framework for Conversion from Binary to Residue Numbers,” IEEE Trans. Circuits and Systems II, Vol. 49, No. 2, pp. 135-144, Feb. 2002. Cites the 1994 VLSI Signal Processing VII paper [98].

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Prusinkiewicz, P., Review #94038, Mathematical Reviews, Vol. 1980a, p. 473, 1980. Review of the IEEETC 1978 arithmetic error code paper [28].

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Qadah, Ghassan Z., “Database Machines: A Survey”, AFIPS Conf. Proc. (1985 Nat’l Computer Conf.), 1985, pp. 211-223. Cites the 1972 RAPID paper [2].

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Rajagopal, S., and J.R. Cavallaro, “Truncated Online Arithmetic with Applications to Communication Systems,” IEEE Trans. Computers, Vol. 55, No. 10, pp. 1240-1252, October 2006. Cites the computer arithmetic book [179].

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Rao, T.R.N. and E. Fujiwara, Error-Control Coding for Computer Systems, Prentice Hall, 1989. Cites the IEEETC 1978 arithmetic error code paper [28] in Ch. 6 on mass memory codes and Ch. 7 on asymmetric and unidirectional codes.

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Roesler, E., and B. Nelson, “Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture,” Proc. 12th Int’l Conf. Field-Programmable Logic and Applications, 2002, LNCS #2438, pp. 637-646. Cites the computer arithmetic book [179].

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Santos, E.S., Review #12217, Mathematical Reviews, Vol. 49, No. 6, p. 2231, June 1975. Review of the IEEETC 1972 stochastic automata paper [1].

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Savas, E., “A Carry-Free Architecture for Montgomery Inversion,” IEEE Trans. Computers, Vol. 54, No. 12, pp. 1508-1519, December 2005. Cites the computer arithmetic book [179].

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Shieh, S.-H., and C.-W. Wu, “Asymmetric High-Radix Signed-Digit Number Systems for Carry-Free Addition,” J. Information Science and Engineering, Vol. 19, pp. 1019-1039, 2003. Cites these five papers: 1988 recoded BSD [56], 1990 GSD [66], 1993 arithmetic support functions [86], 1994 GSD implementation alternatives [99], and 1996 area-efficient multipliers [117].

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Shiva, S.G., Computer Design and Architecture, Marcel Dekker, 3rd ed., 2000. Cites the parallel processing book [162].

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Sivilotti, M., M. Emerling, and C. Mead, “A Novel Associative Memory Implemented Using Collective Computation,” Proc. of the Chapel Hill Conf. on Very Large Scale Integration, Computer Science Press, 1985, pp. 329-342. Cites the Proc. IEEE 1973 survey paper [4].

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Smith, D.C.P. and J.M. Smith, “Relational Database Machines,” IEEE Computer, Vol. 12, No. 3, pp. 28-38, Mar. 1979. Cites the 1972 RAPID paper [2].

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Stuttgen, H.J., A Hierarchical Associative Processing Systems, Springer-Verlag, 1985, p. 32. Uses the classification introduced in the Proc. IEEE 1973 survey paper [4].

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Su, S.Y.W., Database Computers: Principles, Architectures, and Techniques, McGraw-Hill, 1988. Uses the classification introduced in the Proc. IEEE 1973 survey paper [4].

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[Swar04] Swartzlander, E.E., Jr., “High-Speed Computer Arithmetic,” Chapter 22 in Computer Science Handbook, ed. by A.B. Tucker, Chapman & Hall / CRC, 2004, pp. 22-1 to 22-22. Cites the computer arithmetic book [179].
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Tarnick, S., “Single- and Double-Output Embedded Checker Architecture for Systematic Unordered Codes,” J. Electronic Testing, Vol. 21, No. 4, pp. 391-404, August 2005. Cites the 1991 ICCD paper on unidirectional codes [77].

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Tartar, J., “Microprocessor Hardware: An Architectural Overview,” Proc. ACM Annual Conf., pp. 518-526, Jan. 1980. Cites the Proc. IEEE 1973 survey paper [4].

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Tatas, K., G. Koutroumpezis, D. Soudris, and A. Thanailakis, “Architecture Design of a Coarse-Grain Reconfigurable Multiply-Accumulate Unit for Data-Intensive Applications,” Integration: The VLSI Journal, Vol. 40, No. 2, pp. 74-93, February 2007. Cites the computer arithmetic book [179].

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Tenca, A.F., S. Park, and L.A. Tawalbeh, “Carry-Save Representation Is Shift-Unsafe: The Problem and Its Solution,” IEEE Trans. Computers, Vol. 55, No. 5, pp. 630-635, May 2006. Cites the book on computer arithmetic [179]..

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Thornton, M.A., Signed Binary Addition Circuitry with Inherent Even Parity Outputs,” IEEE Trans. Computers, Vol. 46, No. 7, pp. 811-816, July 1997. Cites the 1990 IEEETC GSD paper [66].

[Tind00] Tinder, R.F., Engineering Digital Design, Revised 2nd Edition, Academic Press, 2000. Cites the computer arithmetic book [179] on page 384.
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Turner, P., Review of book on computer arithmetic [179], ACM Computing Reviews,  Oct. 1999. From the review: “Parhami has done an excellent job of presenting the fundamentals of computer arithmetic in a well-balanced, careful, and organized manner. The care taken by the author is borne out by the almost total absence of typos or incorrect cross-references. I would choose this book as a text for a first course in computer arithmetic.

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Vankka, J., and K. Halonen, Direct Digital Synthesizers: Theory, Design and Applications, Kluwer, 2001. Cites the 1993 IEEETC paper on arithmetic support functions for GSD [86].

[Udre04] Udrescu, M., L. Prodan, and M. Vladutiu, “Using HDLs for Describing Quantum Circuits: A Framework for Efficient Quantum Algorithm Simulation,” Proc. First ACM Conf. Computing Frontiers, Ischia, Italy, April 2004, pp. 96-110. Cites the computer arithmetic book [179].

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Wakerly, J.F., Error Detecting Codes, Self-Checking Circuits and Applications,  North-Holland, New York, 1978. Cites the 1973 FTCS arith. code paper [3].

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Wolf, G., “Associative Mass Storage for Database,” Proc. 5th Workshop Computer Architecture for Non-Numeric Processing, pp. 70-81, Mar. 1980. Cites the Proc. IEEE 1973 survey paper [4].

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Wu, H. and M.A. Hassan, “Efficient Exponentiation of a Primitive Root in GF(2m),” IEEE Trans. Computers, Vol. 46, No. 2, pp. 162-172, February 1997. Cites the 1990 IEEETC paper on GSD representations [66].

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Xie, M., and H. Pham, “Modeling the Reliability of Threshold Weighted Voting Systems,” Reliability Engineering & System Safety, Vol. 87, pp. 53-63, 2005. Cites the 1994 IJRQSE paper on threshold voting [94] and the 1994 IEEETR paper on voting algorithms [101].

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Xu, L. and J. Bruck, “Deterministic Voting in Distributed Systems Using Error-Correcting Codes,” IEEE Trans. Parallel and Distributed Systems, Vol. 9, No. 8, pp. 813-824, August1998. Cites the 1994 IEEETR paper on voting algorithms [101].

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Yacoub, S., “Analyzing the Behavior and Reliability of Voting Systems Comprising Tri-State Units Using Enumerated Simulation,” Reliability Engineering & System Safety, Vol. 81, pp. 133-145, 2003. Cites the 1994 IJRQSE paper on threshold voting [94] and the 1994 IEEETR paper on voting algorithms [101].

[Yahy92]

Yahya, A.H., “Local Considerations in Computer Science Curricula Development,” ACM SIGCSE Bulletin (Proc. 23rd Technical Symp. Computer Science Education), Vol. 24, No. 1, pp. 123-128, Mar. 1992. Cites the Education & Computing 1986 paper on CSE education in Iran [47].

[Yang04] Yang, X., D.J. Evans, H. Lai, and G.M. Megson, “Generalized Honeycomb Torus is Hamiltonian,” Information Processing Letters, Vol. 92, pp. 31-37, 2004. Cites the parallel processing book [162] and the 2001 IEEETPDS paper on honeycomb and diamond networks [191].
[Yang05] Yang, X., G.M. Megson, Y. Tang, and D.J. Evans, “Diameter of Parallelogramic Honeycomb Torus,” Computers and Mathematics with Applications, Vol. 50, Nos. 8-9, pp. 1477-1486, October 2005. Cites the book on parallel processing [162] and the 2001 IEEE TPDS paper on honeycomb and diamond networks [191].
[Yang06] Yang, X., G.M. Megson, and D.J. Evans, “An Oblivious Shortest-Path Routing Algorithm for Fully Connected Cubic Networks,” J. Parallel and Distributed Computing, Vol. 66, No. 10, pp. 1294-1303, October 2006. Cites the 1996 ICPDS paper on swapped networks [119], the parallel processing book [162], and the 2005 IPL and JPDC papers on swapped networks [222], [224].
[Yang07] Yang, X., G.M. Megson, X. Liao, and J. Cao, “Generalized Matching Networks and Their Properties,” Int'l J. Parallel, Emergent, and Distributed Systems, Vol. 22, No. 3, pp. 185-192, June 2007. Cites the book on parallel processing [162] and the 2005 IPL and JPDC papers on swapped networks [222], [224].

[Yau77]

Yau, S.S. and H.S. Fung, “Associative Processor Architecture -- A Survey,” ACM Computing Surveys, Vol. 9, No. 1, pp. 3-27, Jan. 1977. Cites the 1972 RAPID paper [2] and the Proc. IEEE 1973 survey paper [4].

[Yell99]

Yellman, T.W., “Failures and Related Topics,” IEEE Trans. Reliability, Vol. 48, No. 1, pp. 6-8, March 1999. Cites the 1997 IEEETR note on fault tolerance terminology [150].

[Yeh98] Yeh, C.-H. and E.A. Varvarigos, “Macro-Star Networks: Efficient Low-Degree Alternatives to Star Graphs,” IEEE Trans. Parallel and Distributed Systems, Vol. 9, No. 10, pp. 987-1003, October 1998. Cites the 1996 paper on hierarchical swapped networks [132], the 1997 paper on cyclic networks [141], and the book on parallel processing [162].
[Yeh02] Yeh, C.-H., “AT2L2 » N2/2 for Fast Fourier Transform in Multilayer VLSI,” Proc. 14th Symp. Parallel Algorithms and Architectures, August 2002, pp. 145-146. Cites a number of papers on VLSI layout and packaging [164], [185], [186].
[Yeh04] Yeh, C.-H., “Optimal Layout for Fast Fourier Transform in Multilayer VLSI,” Proc. Int’l Parallel and Distributed Processing Symp., Santa Fe, NM, 2004. Cites a number of papers on VLSI layout and packaging [159], [164], [167], [185], [186], [193].

[Yeo04]

Yeo, K.-S., and K. Roy, Low Voltage, Low Power VLSI Subsystems, McGraw-Hill, 2004. Cites the computer arithmetic book [179].

[Yu01]

Yu, F.T.S., S. Jutamulia, and S. Yin, Introduction to Information Optics, Academic Press, 2001. Cites the 1988 IEEETC paper on recoded BSD addition [56].

[Zaky77]

Zaky, S.G., “Microprocessors for Non-Numeric Processing,” Proc. 3rd Workshop Computer Architecture for Non-Numeric Processing, pp. 23-30, Jan. 1977. Cites the Proc. IEEE 1973 survey paper [4].

      

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Dr. Behrooz Parhami, Professor

                     Office phone: +1 805 893 3211
E-mail: parhami@ece.ucsb.edu                 Messages: +1 805 893 3716
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