PhD Defense: "Soft Error Mitigation Studies"

Di Wang

March 16th (Wednesday), 3:00pm
Engineering Science Building (ESB), Room 2001 (ESB Conf. Rm.)

Soft error rate increases exponentially with the scaling of CMOS technology, and nowadays soft error induces product failure rates in commercial electronics that are higher than all the other reliability mechanism combined. Soft error rate has become a design parameter along with speed, power, area, and so forth.

Conventionally mitigation techniques are applied a posteriori to conquer any possible soft errors. Being unaware of the error properties, designers may over-protect their circuits yet still see errors in the end due to ineffective strategies. This work presents the idea of choosing strategies according to error properties and validating the system-level performance based on error date. This work also include a CAD tool for verification.

Hosted by: Professor Forrest Brewer