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ECE Professor Kaustav Banerjee’s research featured in the UCSB Current article “Building An Ideal MOSFET”

May 28th, 2020

photo of a chip
Prof. Kaustav Banerjee and ECE researchers demystify the role of negative capacitance in modern MOSFETs after over a decade since its conception

As our electronics continue to proliferate and become more sophisticated, the race continues for more power efficient and scaleable semiconductor devices — components that use minimal power while being small enough to pack into increasingly dense integrated circuits.

MOSFETs (metal-oxide field-effect transistors) are an example of such a breakthrough. Developed in the 1960s, their low power consumption, scalability, compactness and ease of mass manufacture made them the go-to logic switch for a wide array of electronics. The rapid miniaturization and densification of these transistors (without a concurrent increase in power consumption) was what led Intel executive Gordon Moore to formulate his famous law: that the number of transistors in an integrated circuit would double every two years. The result has been a steady increase in the performance of our computers for several decades, from desktops and laptops to our smart devices and wearables. Today’s smartphones have billions of nanoscale MOSFETs.

However, the benefits of downward scaleability — at least in terms of conventional FETs — seems to be hitting a limit, according to UC Santa Barbara electrical and computer engineering professor Kaustav Banerjee, a renowned expert in nanoelectronics and one of the world’s most influential scientific minds, according to Clarivate Analytics. And though a certain type of transistor called a negative-capacitance FET (NC-FET) has been touted as a way to maintain performance, Banerjee thinks it’s time to reconsider its role.

“After over a decade of misconception and confusion in the scientific community, we have essentially blasted the myth that NC-FET is a steep-slope device,” Banerjee said of his paper, “Is negative capacitance FET a steep-slope logic switch?,” recently published in Nature Communications.

The UCSB Current – "Building An Ideal MOSFET" (full article)

Banerjee's COE Profile

Banerjee's Nanoelectronics Research Lab