I am a researcher across chip design, design automation, and computer architecture regions. My recent research topics are:
Processing-In-Memory (PIM) and Near Data Processing (NDP) Architecture:
We design PIM/NDP to embrace hidden bandwidth and reduce data movement overhead. Our architectures bridge technologies of both off-the-shelf DRAM and emerging NVM with killer applications such as deep learning, bioinformatics.
- Chip fabricated; Code release; Many publications on ISCA'16, MICRO'17/18, IEDM'17, etc.
Memory Architecture Optimization for Big Data Applications:
We optimize the whole memory system pipeline (scratchpad memory, cache, memory controller, ...) for various big data applications, such as (dynamic) graph analytic, persistent database, blockchain, homomorphic encryption.
- Publications on DAC'18, CAL'18, MICRO'18, etc.
Non-Von Neumann Architecture for Deep Neural Network:
We adopt algorithm-architecture co-design approaches for DNN accelerators, with emphasis on memory system. Our scope also includes emerging technology, neuromorphic computing, compiler, and design automation.
- Publications on ISCA'16, MICRO'16, TPDS'18, etc.
Previous/Other research topics:
Non-volatile Processor Architecture and Chip Design for IoT:
We leverage NVM for robust processor's circuit, architecture, and system design, dedicated for self-powered IoT devise.
- Chip fabricated; Publications on ESCIRC'12, HPCA'15, IEEE MICRO'16.
- HPCA best paper; Micro Top Pick 2016; ISLPED'12 design contest winner.
System Optimization for High-level Synthesis:
This project optimizes high-level synthesis design flow with user-defined constraints and objectives.
- Publications on ASP-DAC'13, TODEAS'15, ISLPED'15, etc; ASP-DAC'13 best paper candidate.