University of California,
Santa Barbara
Department of Electrical and Computer Engineering
CMOS Analog VLSI I
ECE 194A/594A Fall 2008
Instructor: Prof. Luke Theogarajan
Schedule:Mondays & Wednesdays 10-11:50 a.m. in the Cooper Lab, Rm 1003, ESB
Analog VLSI is an important part of a circuit designer’s repertoire and is essential to building any system which interfaces to sensors or signals in the real world. Additionally, CMOS Analog design is regarded as a “magical art” and this course is intended to demystify this uniquely intuitive field. Students will develop an intuitive understanding to designing analog circuits and perform “back-of-the-envelope” calculation to sizing designs. Extensive use of industry standard tools such as CADENCE will be used for the design projects in this course. This course will highlight the unique design issues and advantages of IC design over discrete circuit design.
Introduction to analog VLSI design assumes some previous exposure to semiconductor devices, feedback theory and basic circuit principles. Topics covered include: Basic physics of MOS transistors, thermal noise and flicker noise, analog layout techniques, current source design, cascode current sources, single transistor amplifiers, active vs. passive loads, the differential amplifier, design of robust bias networks, two stage op-amp design, compensation techniques for the two-stage op-amp, fully differential op-amp design, design of common-mode feedback loops. The class involves two projects the first will be halfway into the semester and will involve the design of a robust current source network and the second project will be the design and layout of an operational amplifier. There will be a mid-term and no final exam.
Required : Introduction to CMOS OP-AMPs and Comparators - Roubik Gregorian
Recommended: Gray, Hurst, Lewis and Meyer: Analysis and Design of analog integrated circuits, Wiley, 4th Edition
Required: ECE 137A and ECE 137B
Recommended : ECE 132, ECE 147A
Problem Sets
Design Projects
Tutorials
Journal Papers
A 100-MHz 100-dB operational amplifier with multipath nested Miller compensation structure
Eschauzier, R.G.H.; Kerklaan, L.P.T.; Huijsing, J.H.;
Solid-State Circuits, IEEE Journal of
Volume 27, Issue 12, Dec. 1992, Page(s):1709 - 1717
Advances in Reversed Nested Miller Compensation
Grasso, A.D.; Palumbo, G.; Pennisi, S.;
Circuits and Systems I: Regular Papers, IEEE Transactions on
Volume 54, Issue 7, July 2007, Page(s):1459 - 1470
Design guidelines for reversed nested Miller compensation in three-stage amplifiers
Mita, R.; Palumbo, G.; Pennisi, S.;
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Volume 50, Issue 5, May 2003, Page(s):227 - 233
Three-stage large capacitive load amplifier with damping-factor-control frequency compensation
Ka Nang Leung; Mok, P.K.T.; Wing-Hung Ki; Sin, J.K.O.;
Solid-State Circuits, IEEE Journal of
Volume 35, Issue 2, Feb. 2000, Page(s):221 - 230
Multistage amplifier topologies with nested Gm-C compensation
You, F.; Embabi, S.H.K.; Sanchez-Sinencio, E.;
Solid-State Circuits, IEEE Journal of
Volume 32, Issue 12, Dec. 1997, Page(s):2000 - 2011
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Last Updated: November 24, 2008