Department of
Electrical and Computer Engineering
Digital Design Principles
ECE 152A - Fall 2005
Prof.
Volkan Rodoplu
Lectures: Tuesday/Thursday
Office hours: Friday
Midterm
Exam:
Final Exam: Look up schedule in course offerings.
Announcements
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12/1/05: There will be a
make-up lecture (review session) for the lecture on 12/1/05. Possible times
& dates for the make-up lecture are: 4:00-5:15 PM Friday (12/2/05) or
5:00-6:15 PM Sunday (12/4/05). However, this is not confirmed yet. Check here
for updates. All the homeworks that were not picked up during the quarter
will be available for pick-up at this make-up lecture. 11/28/05: Prof. Rodoplu
will not have office hours on December 2, 2005. Please ask your questions
during or after the review lectures this week. 11/18/05: There will be no
review session on 11/23/05, the day before Thanksgiving. 11/14/05: Lecture slides of
the 11/10/05 lecture has been posted as "Timing_Supplement2" under
Lecture Notes. 11/11/05: The lecture
slides of the 11/10/05 lecture will be posted on 11/14/05 (since they need to
be scanned). All the other new lecture notes have been posted below. 11/08/05: The deadline of
HW # 5 has been changed from Nov. 29, 2:00 PM to Dec. 1, 2:00 PM. 11/04/05: Reading for Lab
5: Chapter 8.5 (Serial Adder) in textbook B & V. 11/04/05: HW # 4 deadline
has been changed from Nov. 15 (Tuesday) 2:00 PM, to Nov. 17 (Thursday) 2:00
PM. 11/04/05: You can always
find the most up-to-date version of the course calendar under the Syllabus
link above. 10/28/05: For HW # 3:
Please type your Verilog code for the problems, if your writing is less than
legible. (You may also run your code through the compiler, although this is
not required for these homework problems.) 10/27/05: The deadline of
HW # 3 has been moved to Nov 10, 2005, Thursday, 2:00 PM. 10/27/05: VERY IMPORTANT
ANNOUNCEMENT: FOR LAB # 4: ONLY PART 1 IS DUE NEXT WEEK. (Initial Lab # 4
statement said Parts 1 and 2 were due, but this was a mistake, and it is now
corrected in the Lab Handout. We have just started discussing Verilog for
sequential machines, so Parts 2, 3 and 4 will be due together at the end.) 10/26/05: A new homework
has been created: Homework 2.5 is due 11/01/05 Tuesday by 2:00 PM in the
Homework Box: Do Problems 1-10 of the ECE 152A
Midterm Fall 2005. (Note: Problems 11-13 are optional.) You MAY work in teams
of 2 people (but you don't have to). FEEL FREE TO DISCUSS ALL PROBLEMS ON HW
2.5 WITH OTHER STUDENTS OUTSIDE YOUR TEAM, SENIOR STUDENTS, TA'S BEFORE YOU
WRITE UP YOUR SOLUTIONS. Each team hands in only 1
solution (this applies to ONLY this special homework). WRITE DOWN THE NAMES OF BOTH PEOPLE IN
THE TEAM AT THE BEGINNING OF YOUR HOMEWORK. Grading: This homework is worth
120 points in your Homework score if you hand in "solid work"
(which is defined as having at least 85% of the answers correct). Otherwise,
no points will be given. The ECE 152A Fall 2005 Midterm
Exam problems have been posted below under the Sample Exams section on this
page. 10/23/05: The calendar in
the syllabus has been updated: The lecture on state minimization has been replaced
by more examples of Mealy/Moore machines and Verilog. 10/21/05: The following
corrections were made to HW # 2 Solutions: Problem 15(b): The Q should
go on for longer. The correct solution appears in the Solutions file now. B&V Problem 7.32: A more
accurate waveform now appears in the revised solutions. 10/20/05: The solution of
Brown & Vranesic, Problem 7.32 (in PDF format) has been placed next to HW
# 2 Solutions. 10/12/05: See the review
session schedule and locations below under "Review Sessions". 10/09/05: IMPORTANT
ANNOUNCEMENT FOR LABORATORY 3: 1) Parts 4 and 5 have been
dropped from Laboratory 3. You will complete only Parts 1, 2 and 3. 2) There is NO pre-lab due
the week of October 17. 3) Parts 1, 2, and 3 (which
are all written parts) will be due at the check-out in the beginning of your
laboratory section, in the week of October 24. 4) The syllabus link has
been revised to reflect these changes. 10/09/05: Course Reader
Problem 17 has been moved from HW#2 to HW#3. (The files for HW#2 and HW#3
below have accordingly been updated.) 10/07/05: FOR LABORATORY 2:
1) For PreLab: Assume (as
we did in class), that every logic gate has a delay of 1 unit. Use this in
your delay analysis. (That is, you do NOT need to use the actual nanosecond
delays of individual gates.) 2) Although we asked you to
do the area and delay analysis in your prelab by examining the minimum sum of products expressions (for
sum and cout), when it comes to your Verilog implementation, you MAY use XOR
gates in your Verilog implementation, if you would like. 3) FOR CHECK-OUT: IN
ADDITION TO YOUR DEMO, PRINT OUT A COPY OF YOUR VERILOG CODE AND SUBMIT IT TO
THE TA. 09/26/05: The syllabus has
been updated to Revision 4. 09/23/05: The syllabus has
been updated (to Revision 3). 09/23/05: MONDAY MORNING
SECTION: For the week of September 26, 2005: PLEASE GO TO ANY OF THE
REMAINING LISTED SECTIONS OR THE NEW SECTION: MONDAY 7:00 - 10:00 PM. 09/23/05: The syllabus has been
revised, in particular the course calendar has been revised. See the above
syllabus link. 09/22/05: ALL LABS START in
the week of September 26, 2005. 09/22/05: For Lab # 1:
Please note that NOT all TTL parts are available. See the hyperlink below on
ECE Shop: List of Available Parts (under Lab Handouts). Only these chips are
available in the lab, so plan your TTL implementation accordingly. 09/22/05: Please use TTL
(7400 series) for your labs (not CMOS 4000 series parts!). 09/22/05: For the lab problem
sets, you need to hand in only 1 solution per team (put both team members'
names on your solutions.) 09/22/05: Check in the ECE Shop (Room: 1160, Engineering-I; M-F: 8:00-12:00 and 1:00-4:00) to get the access cards for the Digital lab. |
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(Homework is
assigned from the reader.)
CourseReader_Problems
10 to 14
Homework - Solutions
The homework is due in
the ECE 152A Homework Box on the 5th floor of Engineering I.
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(due October 11, 2005; 2:00 PM) |
(due October 18, 2005; 2:00 PM) (due November 1, 2005; 2:00 PM) |
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(due November 10, 2005; 2:00 PM) (Deadline has been changed from Nov. 8 to
Nov. 10.) |
(due November 17, 2005; 2:00 PM) |
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(due December 1, 2005; 2:00 PM) |
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Grading
Guidelines for Homeworks and Labs
Lab Handouts
Lab Schedule
Print out Data Sheets for each lab
Import libraries into
Modelsim
ECE Shop: List of
Available Parts
ALL PRE-LABS DUE ARE AT THE BEGINNING OF
YOUR LAB.
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Pre-lab due: |
Pre-lab due: Check-out: October 17, 2005 |
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Lab starts: October 17, 2005 Pre-lab: NO PRE-LAB DUE Check-out: October 24, 2005 (Note:
Only Parts 1, 2, and 3 will be due at the check-out. Parts 4 and 5 have been
dropped from this laboratory.) |
Lab # 4 Lab-4 help Sample C program cbw.h cbw32bc.lib
lab4_verilog Sample-Testbench Lab starts: (There is no pre-lab for this lab.) Part 1 due: Parts 2, 3 and 4 due: November 7, 2005 |
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Lab starts: (There is no pre-lab
for this lab.) Parts 1 and 2 due: Parts 3 and 4 due:
November 21, 2005 |
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Lab
Sections and TA Office Hours
Engr
I, Room 1124 (DigiLab)
You may go
to the office hours of any TA (not just the TA of your lab section)
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Sean Gordoni Lab Section: Tue 700PM~950PM Office hours: Tue 1200PM~200PM |
Saeed Mirzaeian Lab Section: Mon 200PM~450PM Office hours: Mon 1200PM~200PM |
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Roopa Chari Lab Section: Mon 700PM~950PM Office hours: Mon 500PM~700PM |
Yi-Wei Lin Lab Section:
Wed 8:00AM~10:50AM Office hours: Fri 10:00AM~12:00PM |
Review Sessions
Location: Webb Hall, Room
1100, starting 10/19/05
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Date |
Time & Place TA |
Location |
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Wednesday |
Roopa |
Engineering I, Room 1104 |
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Wednesday |
Sean |
Engineering I, Room 1104 |
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Wednesday |
Yi-Wei |
Webb Hall, Room 1100 |
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No review session on 10/26/05 |
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11/02/05 |
Saeed |
Webb Hall Room 1100 |
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11/09/05 |
Roopa |
Webb Hall Room 1100 |
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11/16/05 |
Sean |
Webb Hall Room 1100 |
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11/30/05 |
Saeed & Yi-Wei |
Webb Hall Room 1100 |
Acknowledgments: We would like to thank all the professors,
TA's and lecturers, who have created, worked on, used, and revised the
laboratories for this course. A partial list is as follows: Prof. Roger C.
Wood, Christian Schmidt, Prof. Kaustav Banerjee, James Rosenthal, Brian
Simolon, John M. Johnson, Prof. Volkan Rodoplu, Aida Todri, Nilesh Modi, Vishal
Mehta, James Tandon.
Practice Exams
ECE 152A Midterm Exam Fall 2004
ECE152A_Midterm Exam Winter 2005
ECE 152A Midterm Exam Fall 2005
ECE 152A Final Exam Winter 2005
Practice Problems for FSM
Design: PS1 PS2 PS4
Lecture Notes (very rough)
(The following are handwritten
lecture notes that I made while preparing for the lectures. These are very
rough compared to the exposition in class, and were mostly notes to myself.
However, I am providing them here in case you find them useful.)
. Blocking vs. Non-blocking
Assignments
. (Enrichment (not required): Lecture 10)