PhD Defense: "Characterization and Modeling of High Current ESD Phenomenon in DeNMOS"

Amitabh Chatterjee

March 17th (Thursday), 1:00pm
Harold Frank Hall Rm 4164

The continuing scaling trends in CMOS technology and emerging growth area of System-On-Chip in advanced nanometer scale technologies, combined with general trend towards siliconization, makes DeNMOS an extremely critical high voltage VLSI I/O device for integration with low voltage core devices and other mixed signal applications. Moreover, efficiency management of electrical energy production and distribution has led to the idea of a “smart grid,” whereby intelligent use of semiconductor technology to distribute electrical energy in a more efficient and cost saving manner becomes viable. This has necessitated demand for one or more output drivers with a power device that performs a real world function, such as charging or switching a battery, controlling a motor, driving a discrete power device, and so on. However, CMOS process based silicon power devices are particularly vulnerable to ESD events.

The ESD events profoundly impact the yield of smart power integrated circuits. Currently, ESD cells have been developed which meet certain rigorous test standards and can absorb the energy of the test without damaging the internal circuits of the device they are designed to protect.Additionally, many a times power devices themselves are large enough to safely absorb relevant energy, and are able to “self protect” against the ESD strike. Yet the co-ordination between ESD protection cells and the Safe operation area of the power components is a fundamental aspect of ESD protection strategies requires more research, as the efficacy of protection devices depends on the “turn-on” behaviour of parasitic bipolar in the structure and absorption of localised Joule heating.

This challenge has necessitated modeling the complex electrothermal interaction between extracted distributed bipolar and the external circuit. In this work we try to understand the turn-on behavior of parasitic bipolar DeNMOS and its impact on 2D electrostatics and 3D thermal diffusion. We study the high current phenomenon in 1D n-/n+ structures and p/n-/n+ structures, model the high current bipolar turn-on phenomenon in simplified 1D and subsequently 2D and 3D device structures. Then examine the impact of self heating on current induced avalanche injection phenomenon in advanced NMOS transistors via 2D electrothermal modeling, We also study the 2D current crowding behavior in low voltage NMOS and high voltage advanced Drain extend nMOS technology, and show the turn-on of parasitic bipolar in the bulk and impact of regenerative effect in 2D due to space charge buildup under high current density. Upon decoupling the impact of 2D electrostatics and 3D thermal diffusion, we have built a fundamental understanding of temperature dependent ballasting effects.

Hosted by: Professor Forrest Brewer