PhD Defense: "Multi-Gigabit Reception with Time-interleaved Analog-to-Digital Converters"

Sandeep Ponnuru

June 3rd (Friday), 12:00pm
ECE Building 406, Rm 216 (Trailer in front of library)

Indian Refreshments will be served!


In modern communication systems, most of the transceiver functionalities are implemented in digital signal processing (DSP). Driven by the Moore’s law, these DSPs are getting increasingly powerful day-by-day. If we wish to extend this advantage to design low-cost multi-Gigabit systems, the analog-to-digital converter (ADC) presents a bottleneck: ADCs with a high sampling rate and a high output resolution at a reasonable power consumption are not available.

This talk will present the popular time- interleaved (TI) architecture as a promising solution to address the ADC bottleneck. In this architecture, slower (but power-efficient) sub-ADCs are interleaved in parallel to make a fast ADC. However, this architecture suffers from mismatches among the sub-ADCs, and eliminating which requires employing larger transistors, analog adjustments, or dedicated digital mismatch compensation. The talk will present a novel approach, in which mismatch and channel dispersion are compensated jointly, with the performance metric being overall communication link reliability rather than ADC performance.

Henceforth, the talk discusses the benefits of compensating mismatch in the frequency domain for OFDM systems. Further, an iterative, online method for jointly estimating the mismatch and channel parameters is presented which leverages the training overhead already available in communication signals. The talk also discusses scalable mismatch estimation and compensation schemes when the number of interleaved sub-ADCs increases.

About Sandeep Ponnuru:

Sandeep Ponnuru completed his undergraduate studies in Electrical Engineering from Indian Institute of Technology, Kanpur. Currently, he is defending for his PhD degree from University of California, Santa Barbara. His interests are in the broad area of digital communications and electronic circuit design, and specifically in the commercialization of multi-Gigabit communication systems. He is the recipient of Outstanding TA award in ECE department for 2010-2011, ECE Dissertation Fellowship (2011) and QualStar award from Qualcomm Inc (2010).

Hosted by: Professor Upamanyu Madhow