PhD Defense: "Exploring the Emerging Design and Variability Challenges in Multi-Gate CMOS Devices"

Seid Hadi Rasouli

August 22nd (Monday), 1:00pm
Elings Hall (CNSI), Room 1601

Multi-gate CMOS devices (including FinFETs) exhibit superior gate control over the channel region and near-ideal subthreshold characteristics, leading to more energy-efficient circuits and systems. As recently announced by Intel, for the first time in the history of modern electronics, a “non-planar” 3-D device (FinFET) is going to replace the planar CMOS devices for sub-22 nm technology nodes. These 3-D device structures usher several paradigm shifts in the circuit design arena and also require understanding of new static and dynamic variability phenomena to optimize the designs and thereby extract the maximum advantages. In this dissertation, we address some of the key design and variability challenges in multi-gate CMOS devices and circuits.

This research (1) introduces a novel method to quantify the effects of “width quantization” on the power consumption of nanoscale multi-gate circuits and systems, (2) improves the energy efficiency of the FinFET blocks by employing innovative circuit design methods and, (3) identifies and models a new “intrinsic” variability phenomenon and quantifies its impact on the dynamic (bias-temperature-instability) as well as static (quantum threshold-voltage) characteristics of metal-gate FinFETs and other multi-gate devices and analyzes their implications for digital circuits.

More specifically, in this talk, we illustrate an accurate estimation method to quantify the effect of width quantization on the power consumption of multi-gate devices and circuits. Width quantization property of multi-gate devices also restricts the design optimization that is normally achieved via continuous device sizing. Hence, a novel dynamic gate (a key component used in memory designs) will be introduced, which employs the exclusive property of the FinFET devices (capacitive coupling between front- and back- gates) to simultaneously improve the energy-efficiency as well as reliability. Additionally, the difference between independent-gate biasing in FinFET devices and body-biasing in planar devices is highlighted in the design of SRAM and a new 8-transistor FinFET-SRAM is proposed for ultra low-power memory applications.

In order to explore the new variability challenges in ultra short-channel metal-gate based multi-gate devices, a new physical model is formulated, which captures the essential physics behind the “work-function variation” (which is known to be the dominant source of threshold-voltage fluctuation in metal-gate devices). The new model is proved to be much more accurate than all existing models in the literature and can be easily employed for analyzing the reliability and performance of multi-gate circuits and systems. Moreover, the impact of work-function variation on the “bias-temperature-instability” characteristics as well as the “quantum threshold-voltage” of multi-gate devices is modeled and quantified. It is shown that these effects will strongly influence the design, performance and reliability of emerging multi-gate CMOS devices and circuits.

About Seid Hadi Rasouli:

Seid Hadi Rasouli received his Bachelors and Masters degrees in electrical engineering from the University of Tehran, Iran, in 2001 and 2004, respectively. From 2004 to 2006, he was a research assistant and lab instructor at the University of Tehran. He joined the Nanoelectronics Research Laboratory at UC Santa Barbara in January 2007 and is currently a Ph.D. candidate in the ECE department. His current research interests are in the area of exploring the design and variability challenges of multi-gate high-k/metal-gate devices and circuits.

Hosted by: Professor Kaustav Banerjee