"Future ESD Challenges for IC Components and Systems"

Dr. Charvaka Duvvury, Texas Instruments, Dallas and EDS Distinguished Lecturer

September 8th (Thursday), 4:00pm
Elings Hall (CNSI), Room 1601

Component level IC protection against ESD has seriously become a major challenge due to advanced scaling of silicon technologies and the development of complex high speed circuits including the effects of system on chip (SoC) applications. Analog and RF designs pose particular limitations. Simultaneous to these, the IC package technology roadmap for larger high pin count packages and the System in Package (SiP) are making it more complicated to design the expected component level ESD performance while meeting the IO high speed requirements. In addition to the necessary component level ESD protection for safe handling at the IC production areas, the system level ESD protection at the board level during end-user applications is becoming even more critical. An understanding of coupling from the interface pins and cross-coupling between pins of different ICs on the board would be important for system level ESD protection designs. This seminar will address these important topics and give an insight into the strategies for coupling from component to system protection design. A roadmap for ESD and the need for innovative approaches that include advanced simulations will be reviewed.

About Dr. Charvaka Duvvury:

Charvaka Duvvury is a Texas Instruments Fellow working in the Technology Design and Integration Group. He is also a Board of Director for the ESD Association since 1997. He received his Ph.D. in Engineering Science from the University of Toledo and has worked as a post-doctoral fellow in physics at the University of Alberta before joining TI. His work at TI has involved numerous areas including DRAM Circuit Design, Transistor SPICE Modeling, as well as Hot Carrier and ESD Reliability. His current work is on development and company wide support on ESD for the nanometer submicron CMOS technologies. He has published over 140 papers in technical journals and conferences and holds 70 patents. He has co-authored books on hot carriers and ESD. He is a recipient of the Outstanding Contributions Award from the EOS/ESD Symposium (1990), Outstanding Mentor Award from the Semiconductor Research Corporation (1994), numerous Best Paper and Best Presentation awards from the EOS/ESD Symposium as well as the Outstanding Paper Award from the IRPS. He is a contributing Editor for the IEEE Transactions on Device and Materials Reliability (TDMR). He is a co-founder and co-chair of the Industry Council on ESD Target Levels whose mission is to establish safe and realistic component ESD target levels while meeting the silicon technology challenges. Dr. Duvvury is a Fellow of the IEEE.

Hosted by: Professor Kaustav Banerjee