PhD Defense: "Hybrid Silicon Photonic Integrated Circuits"

Geza Kurczveil

February 24th (Friday), 11:00am
Elings Hall, Room 1605

Silicon photonics promises the low cost integration of optical components with CMOS electronics thus enabling optical interconnects in future generation processors. The hybrid silicon platform (HSP) is one approach to make optically active components on silicon. While many optical components on the HSP have been demonstrated, few photonic integrated circuits (PICs), consisting of multiple elements, have been demonstrated. In this seminar, two Hybrid Silicon PICs and their building blocks will be presented.
The first PIC to be presented is a multiwavelength laser based on an AWG. It consists of Fabry–Perot cavities integrated with hybrid silicon amplifiers and an intracavity filter in the form of an AWG with a channel spacing of 360 GHz. Four-channel lasing operation is shown. Single-sided fiber-coupled output powers as high as 35 μW are measured. The SMSR is as high as 35 dB. Various device characteristics are compromised as the AWG was attacked during the III-V process, thus showing the need to properly protect passive components during III-V processing.

The second PIC to be presented is a fully integrated optical buffer. The device consists of a hybrid silicon switch, a 1.1 m long silicon waveguide, and cascaded hybrid silicon amplifiers. The passive delay line is protected by dielectric layers to limit passive losses to 0.5 dB/cm. Noise filters in the form of saturable absorbers are integrated in the buffer to allow for a larger number of recirculations in the delay line compared to a delay without filters. Tapers are used to transition the mode from the passive region to the hybrid region with losses as low as 0.22 dB per transition and reflectivities below -35 dB. Error free operation of the hybrid silicon switch is demonstrated in all four paths. The integrated buffer failed due to low yield, showing the current limitations of the HSP.

Hosted by: Professor John E. Bowers